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公开(公告)号：US20220367462A1
公开(公告)日：2022-11-17
申请号：US17872907
申请日：2022-07-25
发明人： Kuo-Cheng Chiang , Shi Ning Ju , Kuan-Lun Cheng , Chih-Hao Wang
IPC分类号： H01L27/092 , H01L29/78 , H01L21/8234 , H01L29/66
摘要： The present disclosure provides a semiconductor structure that includes a substrate having a frontside and a backside; an active region extruded from the substrate and surrounded by an isolation feature; a gate stack formed on the front side of the substrate and disposed on the active region; a first and a second source/drain (S/D) feature formed on the active region and interposed by the gate stack; a frontside contact feature disposed on a top surface of the first S/D feature; a backside contact feature disposed on and electrically connected to a bottom surface of the second S/D feature; and a semiconductor layer disposed on a bottom surface of the first S/D feature with a first thickness and a bottom surface of the gate stack with a second thickness being greater than the first thickness.
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公开(公告)号：US20220359725A1
公开(公告)日：2022-11-10
申请号：US17874031
申请日：2022-07-26
发明人： Jia-Ni Yu , Kuo-Cheng Chiang , Lung-Kun Chu , Chung-Wei Hsu , Chih-Hao Wang , Mao-Lin Huang
IPC分类号： H01L29/66 , H01L21/8238 , H01L27/092 , H01L29/78
摘要： Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a gate dielectric layer around first channel layers in a p-type gate region and around second channel layers in an n-type gate region. Sacrificial features are formed between the second channel layers in the n-type gate region. A p-type work function layer is formed over the gate dielectric layer in the p-type gate region and the n-type gate region. After removing the p-type work function layer from the n-type gate region, the sacrificial features are removed from between the second channel layers in the n-type gate region. An n-type work function layer is formed over the gate dielectric layer in the n-type gate region. A metal fill layer is formed over the p-type work function layer in the p-type gate region and the n-type work function layer in the n-type gate region.
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公开(公告)号：US20220320348A1
公开(公告)日：2022-10-06
申请号：US17843332
申请日：2022-06-17
IPC分类号： H01L29/786 , H01L29/06 , H01L29/423 , H01L29/66 , H01L21/3065 , H01L21/311 , H01L21/02
摘要： A method of forming a semiconductor device includes forming a fin of alternating layers of semiconductor nanostructures and sacrificial layers, laterally etching sidewall portions of the sacrificial layers, and depositing additional semiconductor material over the sidewalls of the semiconductor nanostructures and sacrificial layers. Following deposition of a dielectric material over the additional semiconductor material and additional etching, the remaining portions of the semiconductor structures and additional semiconductor material collectively form a hammer shape at each opposing side of the fin. Epitaxial source/drain regions formed on the opposing sides of the fin will contact the heads of the hammer shapes.
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公开(公告)号：US20220310841A1
公开(公告)日：2022-09-29
申请号：US17838941
申请日：2022-06-13
发明人： Shi Ning Ju , Kuo-Cheng Chiang , Chih-Hao Wang , Kuan-Lun Cheng
IPC分类号： H01L29/78 , H01L23/522 , H01L23/528 , H01L21/8234 , H01L27/092 , H01L29/66 , H01L21/768 , H01L29/417 , H01L27/088
摘要： A semiconductor structure includes a power rail on a back side of the semiconductor structure, a first interconnect structure on a front side of the semiconductor structure, and a source feature, a drain feature, a first semiconductor fin, and a gate structure that are between the power rail and the first interconnect structure. The first semiconductor fin connects the source feature and the drain feature. The gate structure is disposed on a front surface and two side surfaces of the first semiconductor fin. The semiconductor structure further includes an isolation structure disposed between the power rail and the drain feature and between the power rail and the first semiconductor fin and a via penetrating through the isolation structure and connecting the source feature to the power rail.
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25.发明授权公开(公告)号：US11456368B2
公开(公告)日：2022-09-27
申请号：US16547994
申请日：2019-08-22
发明人： Kuo-Cheng Chiang , Kuan-Ting Pan , Huan-Chieh Su , Shi-Ning Ju , Chih-Hao Wang
IPC分类号： H01L29/423 , H01L29/78 , H01L29/06 , H01L29/66 , H01L21/308
摘要： A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a substrate, and a hard mask layer formed over the fin structure. The semiconductor device structure also includes a gate structure formed surrounding the hard mask layer and the fin structure, and a portion of the gate structure is interposed between the fin structure and the hard mask layer. The semiconductor device structure further includes a source/drain (S/D) structure formed adjacent to the gate structure.
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公开(公告)号：US11450662B2
公开(公告)日：2022-09-20
申请号：US16952812
申请日：2020-11-19
IPC分类号： H01L27/088 , H01L29/786 , H01L21/8234 , H01L29/423
摘要： A semiconductor device according to the present disclosure includes a first gate structure and a second gate structure aligned along a direction, a first metal layer disposed over the first gate structure, a second metal layer disposed over the second gate structure, and a gate isolation structure extending between the first gate structure and the second gate structure as well as between the first metal layer and the second metal layer.
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27.发明授权公开(公告)号：US11444170B1
公开(公告)日：2022-09-13
申请号：US17199629
申请日：2021-03-12
发明人： Chih-Chao Chou , Kuo-Cheng Chiang , Shi Ning Ju , Wen-Ting Lan , Chih-Hao Wang
IPC分类号： H01L29/423 , H01L29/66 , H01L29/08 , H01L29/10
摘要： Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.
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公开(公告)号：US11430892B2
公开(公告)日：2022-08-30
申请号：US16704110
申请日：2019-12-05
发明人： Kuo-Cheng Chiang , Zhi-Chang Lin , Shih-Cheng Chen , Chih-Hao Wang , Pei-Hsun Wang , Lo-Heng Chang , Jung-Hung Chang
IPC分类号： H01L29/78 , H01L29/66 , H01L29/417
摘要： A semiconductor device and a method of forming the same are provided. A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a first semiconductor channel member and a second semiconductor channel member extending between the first and second source/drain features, and a first dielectric feature and a second dielectric feature each including a first dielectric layer and a second dielectric layer different from the first dielectric layer. The first and second dielectric features are sandwiched between the first and second semiconductor channel members.
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公开(公告)号：US11387346B2
公开(公告)日：2022-07-12
申请号：US16858440
申请日：2020-04-24
发明人： Mao-Lin Huang , Lung-Kun Chu , Chung-Wei Hsu , Jia-Ni Yu , Kuo-Cheng Chiang , Chih-Hao Wang
IPC分类号： H01L29/66 , H01L29/06 , H01L29/10 , H01L29/786
摘要： A method includes providing first and second channel layers in a p-type region and an n-type region respectively, forming a gate dielectric layer around the first and second channel layers, and forming a sacrificial layer around the gate dielectric layer. The sacrificial layer merges in space between the first channel layers and between the second channel layers. The method further includes etching the sacrificial layer such that only portions of the sacrificial layer in the space between the first channel layers and between the second channel layers remain, forming a mask covering the p-type region and exposing the n-type region, removing the sacrificial layer from the n-type region, removing the mask, and forming an n-type work function metal layer around the gate dielectric layer in the n-type region and over the gate dielectric layer and the sacrificial layer in the p-type region.
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公开(公告)号：US11205711B2
公开(公告)日：2021-12-21
申请号：US16583388
申请日：2019-09-26
IPC分类号： H01L29/66 , H01L21/306 , H01L29/08 , H01L21/02 , H01L29/06 , H01L29/78 , H01L29/423 , H01L27/11 , H01L29/10
摘要： A semiconductor device according to the present disclosure includes first gate-all-around (GAA) devices in a first device area and second GAA devices in a second device area. Each of the first GAA devices includes a first vertical stack of channel members, a first gate structure over and around the first vertical stack of channel members, and a plurality of inner spacer features. Each of the second GAA devices includes a second vertical stack of channel members and a second gate structure over and around the second vertical stack of channel members. Two adjacent channel members of the first vertical stack of channel members are separated by a portion of the first gate structure and at least one of the plurality of inner spacer features. Two adjacent channel members of the second vertical stack of channel members are separated only by a portion of the second gate structure.
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