公开(公告)号：US20190355835A1

公开(公告)日：2019-11-21

申请号：US16528768

申请日：2019-08-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching CHENG ,  Wei-Sheng YUN ,  Shao-Ming YU ,  Tsung-Lin LEE ,  Chih-Chieh YEH

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L29/786 ,  H01L29/775

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a plurality of nanowires over an input-output region, and a protective layer surrounding the nanowires. The protective layer is made of silicon, silicon germanium, silicon oxide, silicon nitride, silicon sulfide, or a combination thereof. The semiconductor device structure also includes a high-k dielectric layer surrounding the protective layer, and a gate electrode surrounding the high-k dielectric layer. The semiconductor device structure further includes a source/drain portion adjacent to the gate electrode, and an interlayer dielectric layer over the source/drain portion.

公开(公告)号：US20190067452A1

公开(公告)日：2019-02-28

申请号：US15692124

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching CHENG ,  Wei-Sheng YUN ,  Shao-Ming YU ,  Tsung-Lin LEE ,  Chih-Chieh YEH

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L29/66666 ,  H01L21/76205 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/78696

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes providing a substrate having a base portion and a fin portion over the base portion. The fin portion has a channel region and a source/drain region. The method also includes forming a stack structure over the fin portion. The stack structure includes first and second semiconductor layers. The method also includes forming a source/drain portion in the stack structure at the source/drain region, and removing a portion of the second semiconductor layer in the channel region in an etching process. The remaining portion of the first semiconductor layer in the channel region forms a nanowire. The method further includes forming a gate dielectric layer surrounding the nanowire, forming a high-k dielectric layer surrounding the gate dielectric layer, and forming a gate electrode surrounding the high-k dielectric layer.

公开(公告)号：US20190067111A1

公开(公告)日：2019-02-28

申请号：US15692768

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Yi TSAI ,  Yen-Ming CHEN ,  Tsung-Lin LEE ,  Chih-Chieh YEH

IPC: H01L21/8234 ,  H01L27/088

Abstract: A fin field effect transistor (FinFET) device structure with dummy fin structures and method for forming the same are provided. The FinFET device structure includes an isolation structure over a substrate and a first fin structure extended above the isolation structure. The FinFET device structure includes a second fin structure embedded in the isolation structure and a liner layer formed on sidewalls of the first fin structures and sidewalls of the second fin structures. The FinFET device structure also includes a material layer formed over the second fin structures, and the material layer and the isolation structure are made of different materials.