公开(公告)号：US20190245065A1

公开(公告)日：2019-08-08

申请号：US16390172

申请日：2019-04-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Sheng CHEN ,  Cheng-Hsien WU ,  Chih-Chieh YEH

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/739 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L21/28518 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6681 ,  H01L29/7391 ,  H01L29/775

Abstract: A device includes a substrate, a first doping portion, a second doping portion, a channel, a semiconductor film, a high-k layer, and a gate. The first doping portion and the second doping portion are over the substrate. The channel is over the substrate and between the first doping portion and the second doping portion. The semiconductor film is around the channel. The high-k layer is around the semiconductor film. The gate is over the high-k layer.

公开(公告)号：US20190139838A1

公开(公告)日：2019-05-09

申请号：US16234916

申请日：2018-12-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Sheng CHEN ,  Tzu-Chiang CHEN ,  Cheng-Hsien WU ,  Chih-Chieh YEH ,  Chih-Sheng CHANG

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L21/02 ,  H01L29/786

Abstract: A semiconductor device includes an n-channel, a p-channel, a first gate dielectric layer, a second gate dielectric layer, a second dielectric sheath layer, and a metal gate. The first gate dielectric layer is around the n-channel. The first dielectric sheath layer is around the first gate dielectric layer. The second gate dielectric layer is around the p-channel. The second dielectric sheath layer is around the second gate dielectric layer, in which the first dielectric sheath layer and the second dielectric sheath layer comprise different materials. The metal gate electrode is around the first dielectric sheath layer and the second dielectric sheath layer.

公开(公告)号：US20180277665A1

公开(公告)日：2018-09-27

申请号：US15590243

申请日：2017-05-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： I-Sheng CHEN ,  Cheng-Hsien WU ,  Chih-Chieh YEH

IPC: H01L29/73 ,  H01L29/10 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/7311 ,  H01L21/28518 ,  H01L27/088 ,  H01L29/1033 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66553

Abstract: A semiconductor device includes a substrate, at least one first semiconductor layer, and at least one second semiconductor layer. The at least one first semiconductor layer is disposed on the substrate, and the at least one second semiconductor layer is disposed on the at least one first semiconductor layer. The at least one first semiconductor layer includes a first doping portion, a second doping portion, a channel, and a semiconductor film. The second doping portion is adjacent to the first doping portion. The channel is disposed between the first doping portion and the second doping portion, and disposed with the substrate in parallel. The semiconductor film is disposed around the channel.

公开(公告)号：US20170062561A1

公开(公告)日：2017-03-02

申请号：US14840904

申请日：2015-08-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Yi PENG ,  Chih-Chieh YEH ,  Hung-Li CHIANG ,  Hung-Ming CHEN ,  Yee-Chia YEO

IPC: H01L29/06 ,  H01L21/322

CPC classification number: H01L29/7853 ,  H01L21/322 ,  H01L21/324 ,  H01L21/823431 ,  H01L23/3171 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/66795 ,  H01L29/785

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The fin structure includes a first surface and a second surface. The first surface is inclined to the second surface. The semiconductor device structure also includes a passivation layer covering the first surface and the second surface of the fin structure. The thickness of a first portion of the passivation layer covering the first surface is substantially the same as that of a second portion of the passivation layer covering the second surface.

Abstract translation: 提供半导体器件结构的结构和形成方法。 半导体器件结构包括在半导体衬底上的鳍结构。 翅片结构包括第一表面和第二表面。 第一表面倾斜于第二表面。 半导体器件结构还包括覆盖翅片结构的第一表面和第二表面的钝化层。 覆盖第一表面的钝化层的第一部分的厚度与覆盖第二表面的钝化层的第二部分的厚度基本相同。

公开(公告)号：US20150162334A1

公开(公告)日：2015-06-11

申请号：US14624782

申请日：2015-02-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jon-Hsu HO ,  Chih-Ching WANG ,  Ching-Fang HUANG ,  Wen-Hsing HSIEH ,  Tsung-Hsing YU ,  Yi-Ming SHEU ,  Chih-Chieh YEH ,  Ken-Ichi GOTO ,  Zhiqiang WU

IPC: H01L27/088 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L27/0924 ,  H01L29/105 ,  H01L29/7831 ,  H01L29/7833 ,  H01L29/785 ,  H01L29/7851

Abstract: A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.

Abstract translation: 形成包括半导体衬底的多栅极半导体器件。 多栅半导体器件还包括第一晶体管，其包括在半导体衬底之上延伸的第一鳍部。 第一晶体管具有形成在其中的第一沟道区。 第一沟道区域包括以第一掺杂剂类型的第一浓度掺杂的第一沟道区域部分和以第一掺杂剂类型的第二浓度掺杂的第二沟道区域部分。 第二浓度高于第一浓度。 第一晶体管还包括形成在第一沟道区上的第一栅电极层。 第一栅极电极层可以是第二掺杂剂类型。 第一掺杂剂类型可以是N型，第二掺杂剂类型可以是P型。 第二沟道区域部分可以形成在第一沟道区域部分上。

公开(公告)号：US20230238451A1

公开(公告)日：2023-07-27

申请号：US18194886

申请日：2023-04-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Sheng YUN ,  Shao-Ming YU ,  Tung-Ying LEE ,  Chih-Chieh YEH

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/66666 ,  H01L29/66787 ,  H01L29/7827 ,  H01L29/0847 ,  H01L29/78642

Abstract: A device includes a plurality of semiconductor fins extending from a substrate. A plurality of first source/drain regions are epitaxially grown from first regions of the semiconductor fins. Adjacent two of the plurality of first source/drain regions grown from adjacent two of the plurality of semiconductor fins are spaced apart by an isolation dielectric. A gate structure laterally surrounds second regions of the plurality of semiconductor fins above the first regions of the plurality of semiconductor fins. A plurality of second source/drain regions are over third regions of the plurality of semiconductor fins above the second regions of the plurality of semiconductor fins.

公开(公告)号：US20210028172A1

公开(公告)日：2021-01-28

申请号：US17066424

申请日：2020-10-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Li CHIANG ,  Szu-Wei HUANG ,  Chih-Chieh YEH ,  Yee-Chia YEO

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L23/528 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/66

Abstract: A semiconductor device includes a first source/drain structure, a channel layer, a second source/drain structure, a gate structure and an epitaxial layer. The channel layer is above the first source/drain structure. The second source/drain structure is above the channel layer. The gate structure is on opposite first and second sidewalls of the channel layer when viewed in a first cross-section taken along a first direction. The gate structure is also on a third sidewall of the channel layer but absent from a fourth sidewall of the channel layer when viewed in a second cross-section taken along a second direction different from the first direction. The epitaxial layer is on the fourth sidewall of the channel layer when viewed in the second cross-section and forming a P-N junction with the channel layer.

公开(公告)号：US20190019888A1

公开(公告)日：2019-01-17

申请号：US15649724

申请日：2017-07-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Sheng YUN ,  Shao-Ming YU ,  Chih-Chieh YEH

IPC: H01L29/78 ,  H01L27/105 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8234

Abstract: A vertical transistor device and a method for fabricating the same are provided. The vertical transistor device includes a semiconductor substrate, first sources/drains and second sources/drains. The semiconductor substrate includes a bottom portion and fin portions located on the bottom portion. Each of the fin portions includes an upper portion and a lower portion. The lower portion is located between the bottom portion of the semiconductor substrate and the upper portion, in which the lower portion includes recesses. The first sources/drains are disposed on terminals of the upper portions of the fin portions. The second sources/drains are disposed on the recesses of the lower portions of the fin portions, in which the sources/drains are not merged with each other. In the method for fabricating the vertical transistor device, the lower portions of the fin portions are patterned to form the recesses on the lower portions of the fin portions.

公开(公告)号：US20180342516A1

公开(公告)日：2018-11-29

申请号：US15605983

申请日：2017-05-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hung-Li CHIANG ,  Szu-Wei HUANG ,  Chih-Chieh YEH ,  Yee-Chia YEO

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/78 ,  H01L23/528 ,  H01L21/8238 ,  H01L21/8234

CPC classification number: H01L27/0922 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/5283 ,  H01L27/0928 ,  H01L29/0649 ,  H01L29/7827

Abstract: A semiconductor device includes a substrate, a well on the substrate and an FFT on the well. The FET includes a first source/drain, a vertical channel layer, a gate structure, a second source/drain and a body structure. The first source/drain is on the well. The vertical channel layer extends form the first source/drain. The first gate structure surrounds a first portion of sidewalls of the vertical channel layer. The second source/drain is on the vertical channel layer. The body structure is in physical contact with the vertical channel layer. The body structure and the vertical channel layer constitute a bipolar device.

公开(公告)号：US20180277658A1

公开(公告)日：2018-09-27

申请号：US15631012

申请日：2017-06-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Sheng YUN ,  Shao-Ming YU ,  Tung-Ying LEE ,  Chih-Chieh YEH

IPC: H01L29/66 ,  H01L29/78

Abstract: A method for manufacturing a semiconductor device is provided by follows. A fin is formed over a substrate. A spacer is formed on a sidewall of a first portion of the fin. An epitaxy feature is grown from a second portion of the fin that is in a position lower than the first portion of the fin, in which the forming the epitaxy feature is performed after the forming the spacer. The spacer is removed to expose the first portion of the fin. A gate stack is formed around the exposed first portion of the fin.