公开(公告)号：US20230238451A1

公开(公告)日：2023-07-27

申请号：US18194886

申请日：2023-04-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Sheng YUN ,  Shao-Ming YU ,  Tung-Ying LEE ,  Chih-Chieh YEH

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/66666 ,  H01L29/66787 ,  H01L29/7827 ,  H01L29/0847 ,  H01L29/78642

Abstract: A device includes a plurality of semiconductor fins extending from a substrate. A plurality of first source/drain regions are epitaxially grown from first regions of the semiconductor fins. Adjacent two of the plurality of first source/drain regions grown from adjacent two of the plurality of semiconductor fins are spaced apart by an isolation dielectric. A gate structure laterally surrounds second regions of the plurality of semiconductor fins above the first regions of the plurality of semiconductor fins. A plurality of second source/drain regions are over third regions of the plurality of semiconductor fins above the second regions of the plurality of semiconductor fins.

公开(公告)号：US20180337034A1

公开(公告)日：2018-11-22

申请号：US15598439

申请日：2017-05-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung-Ying LEE ,  Shao-Ming YU

IPC: H01L21/02 ,  H01L29/16 ,  H01L29/34

CPC classification number: H01L21/0243 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639 ,  H01L29/16 ,  H01L29/34

Abstract: A semiconductor device includes a substrate, a first dielectric layer, a first semiconductor layer, a second dielectric layer and a second semiconductor layer. The first dielectric layer is disposed on the substrate and includes at least one first trench formed in the first dielectric layer. The first semiconductor layer is disposed on the first dielectric layer and within the at least one first trench. The second dielectric layer is disposed on the first semiconductor layer and includes at least one second trench formed in the second dielectric layer, wherein in a planar view, the at least one first trench and the at least one second trench are not overlapped with each other. The second semiconductor layer is disposed on the second dielectric layer and within the at least one second trench.

公开(公告)号：US20140331192A1

公开(公告)日：2014-11-06

申请号：US14338194

申请日：2014-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Ming YU ,  Chang-Yun CHANG

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  G06F2217/12 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10879 ,  H01L27/11 ,  H01L27/1116 ,  H01L29/785

Abstract: A method for designing a semiconductor ic chip includes dividing the chip into functional blocks such as a core portion and one or more other functional cells and applying design rules concerning the spatial arrangement of semiconductor fins to the core portion but not to the other functional cells. The design guidelines include the application of design rules to some but not all functional blocks of the chip, may be stored on a computer-readable medium and the design of the semiconductor ic chip and the generation of a photomask set for manufacturing the semiconductor ic chip may be carried out using a CAD or other automated design system. The semiconductor ic chip formed in accordance with this method includes semiconductor fins that are formed in both the core portion and the other functional cells but are only required to be tightly packed in the core portion.

Abstract translation: 一种用于设计半导体芯片的方法包括将芯片划分为诸如核心部分和一个或多个其它功能单元的功能块，并将关于半导体鳍片的空间布置的设计规则应用于核心部分而不是其它功能单元。 设计指南包括将设计规则应用于芯片的一些而不是所有功能块，可以存储在计算机可读介质上，半导体芯片的设计以及用于制造半导体芯片的光掩模组的生成 可以使用CAD或其他自动化设计系统进行。 根据该方法形成的半导体IC芯片包括形成在芯部和其它功能单元两者中但仅需要紧密堆积在芯部中的半导体散热片。

公开(公告)号：US20240023462A1

公开(公告)日：2024-01-18

申请号：US18475978

申请日：2023-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chao LIN ,  Yuan-Tien TU ,  Shao-Ming YU ,  Tung-Ying LEE

IPC: H10N70/00 ,  H10N70/20

CPC classification number: H10N70/063 ,  H10N70/023 ,  H10N70/231 ,  H10N70/826

Abstract: A phase change random access memory (PCRAM) device includes a memory cell overlying an inter-metal dielectric (IMD) layer, a protection coating, and a first sidewall spacer. The memory cell includes a bottom electrode, a top electrode and a phase change element between the top electrode and the bottom electrode. The protection coating is on an outer sidewall of the phase change element. The first sidewall spacer is on an outer sidewall of the protection coating. The first sidewall spacer has a greater nitrogen atomic concentration than the protection coating. The protection coating forms a first interface with the phase change element. The first interface has a first slope at a first position and a second slope at a second position higher than the first position, the second slope is different from the first slope.

公开(公告)号：US20190355835A1

公开(公告)日：2019-11-21

申请号：US16528768

申请日：2019-08-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching CHENG ,  Wei-Sheng YUN ,  Shao-Ming YU ,  Tsung-Lin LEE ,  Chih-Chieh YEH

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L29/786 ,  H01L29/775

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a plurality of nanowires over an input-output region, and a protective layer surrounding the nanowires. The protective layer is made of silicon, silicon germanium, silicon oxide, silicon nitride, silicon sulfide, or a combination thereof. The semiconductor device structure also includes a high-k dielectric layer surrounding the protective layer, and a gate electrode surrounding the high-k dielectric layer. The semiconductor device structure further includes a source/drain portion adjacent to the gate electrode, and an interlayer dielectric layer over the source/drain portion.

公开(公告)号：US20190103317A1

公开(公告)日：2019-04-04

申请号：US15940329

申请日：2018-03-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Shao-Ming YU ,  Tung Ying LEE ,  Wei-Sheng YUN ,  Fu-Hsiang YANG

IPC: H01L21/8234 ,  H01L21/308 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/165

Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer having a first composition over a semiconductor substrate, and forming a second semiconductor layer having a second composition over the first semiconductor layer. Another first semiconductor layer having the first composition is formed over the second semiconductor layer. A third semiconductor layer having a third composition is formed over the another first semiconductor layer. The first semiconductor layers, second semiconductor layer, and third semiconductor layer are patterned to form a fin structure. A portion of the third semiconductor layer is removed thereby forming a nanowire comprising the second semiconductor layer, and a conductive material is formed surrounding the nanowire. The first semiconductor layers, second semiconductor layer, and third semiconductor layer include different materials.

公开(公告)号：US20190067452A1

公开(公告)日：2019-02-28

申请号：US15692124

申请日：2017-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching CHENG ,  Wei-Sheng YUN ,  Shao-Ming YU ,  Tsung-Lin LEE ,  Chih-Chieh YEH

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L29/66666 ,  H01L21/76205 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/78696

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes providing a substrate having a base portion and a fin portion over the base portion. The fin portion has a channel region and a source/drain region. The method also includes forming a stack structure over the fin portion. The stack structure includes first and second semiconductor layers. The method also includes forming a source/drain portion in the stack structure at the source/drain region, and removing a portion of the second semiconductor layer in the channel region in an etching process. The remaining portion of the first semiconductor layer in the channel region forms a nanowire. The method further includes forming a gate dielectric layer surrounding the nanowire, forming a high-k dielectric layer surrounding the gate dielectric layer, and forming a gate electrode surrounding the high-k dielectric layer.

公开(公告)号：US20190067441A1

公开(公告)日：2019-02-28

申请号：US15725655

申请日：2017-10-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Lin YANG ,  Tung Ying LEE ,  Shao-Ming YU ,  Chao-Ching CHENG ,  Tzu-Chiang CHEN ,  Chao-Hsien HUANG

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/764 ,  H01L21/311 ,  H01L21/3115

CPC classification number: H01L29/4991 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/764 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78618 ,  H01L29/78696

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. A first insulating layer is formed, in the source/drain space, at least on etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space, thereby forming air gaps between the source/drain epitaxial layer and the first semiconductor layers.

公开(公告)号：US20230380305A1

公开(公告)日：2023-11-23

申请号：US18362770

申请日：2023-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung-Ying LEE ,  Shao-Ming YU ,  Yu-Chao LIN

IPC: H10N70/20 ,  H10N70/00

CPC classification number: H10N70/231 ,  H10N70/8828 ,  H10N70/826 ,  H10N70/841 ,  H10N70/011

Abstract: A device includes a bottom electrode, a first memory layer, a second memory layer, and a top electrode. The bottom electrode is over a substrate. The first memory layer is over the bottom electrode. A sidewall of the first memory layer is curved. The second memory layer is over the bottom memory layer. The top electrode is over the top memory layer.

公开(公告)号：US20220209106A1

公开(公告)日：2022-06-30

申请号：US17695704

申请日：2022-03-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung-Ying LEE ,  Shao-Ming YU ,  Yu-Chao LIN

IPC: H01L45/00

Abstract: A phase change memory device includes a bottom conductive line, a dielectric layer, a bottom memory layer, and a top electrode. The dielectric layer covers the bottom conductive line. The bottom memory layer is in the dielectric layer and is electrically connected to the bottom conductive line. The bottom memory layer includes a tapered portion and a neck portion. The tapered portion is over the bottom conductive line and is tapered toward the bottom conductive line. The neck portion is directly between the tapered portion and the bottom conductive line. The neck portion has a substantially constant width. The top electrode is over and electrically connected to the bottom memory layer.