公开(公告)号：US11320488B2

公开(公告)日：2022-05-03

申请号：US17160461

申请日：2021-01-28

Applicant: Texas Instruments Incorporated

Inventor： Sundarrajan Rangachari ,  Saket Jalan

IPC: G01R31/319 ,  G01R31/317 ,  G01R31/3177

Abstract: Methods and apparatus for self test of safety logic in safety critical devices is provided in which the safety logic includes comparator logic coupled to a circuit under test (CUT) in a safety critical device and the self test logic is configured to test the comparator logic. The self test logic may be implemented as a single cycle parallel bit inversion approach, a multi-cycle serial bit inversion approach, or a single cycle test pattern injection approach.

公开(公告)号：US20200210287A1

公开(公告)日：2020-07-02

申请号：US16790444

申请日：2020-02-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saket Jalan ,  Indu Prathapan ,  Abhishek Ganapati Karkisaval

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06

Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic. A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.

公开(公告)号：US10599514B2

公开(公告)日：2020-03-24

申请号：US15844259

申请日：2017-12-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saket Jalan ,  Indu Prathapan ,  Abishek Ganapati Karkisaval

IPC: H03M13/00 ,  G06F11/10 ,  G06F3/06 ,  G11C29/52

Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.

公开(公告)号：US20180239530A1

公开(公告)日：2018-08-23

申请号：US15437253

申请日：2017-02-20

Applicant: Texas Instruments Incorporated

Inventor： Saket Jalan ,  Sudesh Chandra Srivastava ,  Mohammed Nabeel

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/40 ,  G11C11/418 ,  G06F11/10

Abstract: In described examples, an apparatus includes: a set of control registers containing control bits for controlling circuitry coupled to receive register write enable signals and to receive input data; a memory for storing data corresponding to the control bits coupled to receive an address and a memory write enable signal; decode circuitry coupled to output the register write enable signals; a data output bus coupled to receive data from the memory but free from connections to the control registers; and a controller coupled to receive an address, coupled to output the address on an internal address bus, coupled to output a write enable signal, and coupled to output the memory write enable signal, configured to cause data to be written to a selected control register corresponding to the address received, and to cause the data to be contemporaneously stored at a memory location corresponding to the address received.

公开(公告)号：US20160182020A1

公开(公告)日：2016-06-23

申请号：US14581296

申请日：2014-12-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Saket Jalan ,  Abhishek Ganapati Karkisaval

IPC: H03K3/027

CPC classification number: H03K19/1737 ,  H03K3/037

Abstract: A circuit includes a state capture device to capture a logic state of a reset selection cell in response to a logic state input. A cell reset node defines a reset state of the reset selection cell. A selection device passes the captured logic state from the state capture device or the reset state from the cell reset node to an output of the reset selection cell based on a state of a control input to the selection device.

Abstract translation: 电路包括状态捕捉装置，以响应于逻辑状态输入来捕获复位选择单元的逻辑状态。 单元复位节点定义复位选择单元的复位状态。 选择装置基于向选择装置输入的控制状态，将捕捉到的状态从状态捕获装置或复位状态从小区重置节点传送到复位选择小区的输出。

公开(公告)号：US09361027B1

公开(公告)日：2016-06-07

申请号：US14571898

申请日：2014-12-16

Applicant: Texas Instruments Incorporated

Inventor： Saket Jalan ,  Rakesh Channabasappa Yaraduyathinahalli

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F9/30141 ,  G11C7/1009 ,  H03K3/037

Abstract: The present invention is drawn to a register writing mechanism that does not require reading of the data in the register. In accordance with aspects of the present invention, each register is masked with a making bit provided by a masking component. In a first implementation, the first half of the bit registers are masked using data in the second half of the bit registers. In a second implementation, all the bit registers are masked using a masking word generated by the masking component.

Abstract translation: 本发明涉及一种不需要读取寄存器中的数据的寄存器写入机制。 根据本发明的方面，每个寄存器被掩蔽组件提供的制作位掩码。 在第一个实现中，使用位寄存器的后半部分的数据对位寄存器的前半部分进行掩码。 在第二实施例中，使用由掩蔽组件产生的屏蔽字来掩蔽所有位寄存器。

公开(公告)号：US09287876B1

公开(公告)日：2016-03-15

申请号：US14623364

申请日：2015-02-16

Applicant: Texas Instruments Incorporated

Inventor： Saket Jalan ,  Mohammed Nabeel

IPC: H03K19/177 ,  H03K19/173

CPC classification number: H03K19/17724 ,  H03K19/1737 ,  H03K19/17736

Abstract: A device includes a plurality of functional logic blocks, a cascaded arrangement of multiplexers and a digital counter. Each of the plurality of functional logic blocks outputs a signals corresponding to nodes to be tested therein. The cascaded arrangement of multiplexers are arranged such that any of the outputs from any of the plurality of functional logic blocks may be selected for output. The digital counter is operable to control the cascaded arrangement of multiplexers so as to output signals from the functional logic blocks based on a counted signal.

Abstract translation: 一种设备包括多个功能逻辑块，多路复用器的级联布置和数字计数器。 多个功能逻辑块中的每一个输出与其中要测试的节点对应的信号。 多路复用器的级联布置被布置成使得可以选择多个功能逻辑块中的任一个的任何输出用于输出。 数字计数器可操作以控制多路复用器的级联布置，以便基于计数的信号从功能逻辑块输出信号。