公开(公告)号：US20220075745A1

公开(公告)日：2022-03-10

申请号：US17530669

申请日：2021-11-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mark Edward Wentroble ,  Suzanne Mary Vining ,  Hassan Omar Ali

IPC: G06F13/40 ,  G06F13/42

Abstract: This disclosure generally relates to USB TYPE-C, and, in particular, DISPLAYPORT Alternate Mode communication in a USB TYPE-C environment. In one embodiment, a device determines a DISPLAYPORT mode and determines an orientation of a USB TYPE-C connector plug. A multiplexer multiplexes a DISPLAYPORT transmission based in part on the determined orientation of the USB TYPE-C connector plug.

公开(公告)号：US11068435B2

公开(公告)日：2021-07-20

申请号：US16751411

申请日：2020-01-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Win Naing Maung ,  Suzanne Mary Vining ,  Yonghui Tang ,  Douglas Edward Wente ,  Huanzhang Huang

IPC: G06F13/42

Abstract: A serial bus signal conditioner circuit includes receiver circuitry, a mode identification circuit, and an edge-rate booster circuit. The receiver circuitry is configured to receive signals transmitted on a serial bus. The mode identification circuit is coupled to the receiver circuitry, and is configured to identify initiation of or return to high-speed signaling on the serial bus based on sequences of the signals transmitted on the serial bus. The edge-rate booster circuit is coupled to the mode identification circuit, and is configured to identify edges of a differential signal transmitted on the serial bus, and to supply a differential current to the serial bus based on identification of an edge of the differential signal.

公开(公告)号：US11068433B2

公开(公告)日：2021-07-20

申请号：US16433661

申请日：2019-06-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Win Naing Maung ,  Suzanne Mary Vining

IPC: G06F13/42 ,  G06F1/3206 ,  G06F13/38

Abstract: A serial bus repeater includes a port circuit and a low power state detection circuit. The port circuit is configured to communicate via a serial bus. The low power state detection circuit includes a power state transaction identification circuit and a bus state identification circuit. The power state transaction identification circuit is configured to identify a power state transaction on the serial bus. The power state transaction is indicative of entering a reduced power state. The bus state identification circuit is configured to identify a value of termination resistance on the serial bus that is indicative of entering the reduced power state.

公开(公告)号：US20200264989A1

公开(公告)日：2020-08-20

申请号：US16661018

申请日：2019-10-23

Applicant: Texas Instruments Incorporated

Inventor： Douglas Edward Wente ,  Suzanne Mary Vining ,  Win Naing Maung ,  Julie Marie Nirchi

IPC: G06F13/10 ,  G06F13/42

Abstract: A method of operating an embedded USB2 (eUSB2) repeater includes receiving a downstream packet at a USB2 port and transitioning a USB transmitter from an idle state to a standby state responsive to receiving the downstream packet. The method further includes transitioning the USB transmitter from the standby state to an active state if an upstream packet is received at an eUSB2 port within a first time period of receiving the downstream packet and transmitting the upstream packet. The method also includes transitioning the USB transmitter from the active state to the standby state after transmission of the upstream packet. The method also includes transitioning the USB transmitter from the standby state to the idle state if more upstream packets are not received at the eUSB2 port within a second time period.

公开(公告)号：US10056151B1

公开(公告)日：2018-08-21

申请号：US15612934

申请日：2017-06-02

Applicant: Texas Instruments Incorporated

Inventor： Suzanne Mary Vining

IPC: G11C16/28 ,  G11C16/32 ,  G11C17/12

CPC classification number: G11C17/12 ,  G06F9/30 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/22 ,  G11C15/00 ,  G11C17/18

Abstract: A multi-read only memory (ROM) state machine circuit includes first and second ROMs (or other memory types), each ROM addressable as a plurality of rows. Each row of the first ROM includes a pointer. Each row of the second ROM includes a set of input compare bits and a next state identifier. A comparator circuit compares each input bit to the state machine circuit to a corresponding bit of the set of input compare bits from the second ROM. A register stores next state identifiers from the second ROM based on the comparator's outputs. Upon receipt of a clock edge, the stored next state identifier from the register is used an address to read a row from the first ROM. The pointer from the first ROM row is then used as an address to read a row from the second ROM. Responsive to the comparator circuit, the next state identifier corresponding to a set of input compare bits that match the input bits to the finite state machine circuit is stored in the register and used as an address to read another row from the first ROM.

公开(公告)号：US12255484B2

公开(公告)日：2025-03-18

申请号：US18429523

申请日：2024-02-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Suzanne Mary Vining

IPC: H01M10/44 ,  G01R19/10 ,  H01M10/46 ,  H02J7/00

Abstract: A method includes determining a charging port mode by receiving a data contact detect (DCD) Complete signal, reducing a voltage on a first data pin of a Universal Serial Bus (USB) connector of a portable device, and determining that a condition is true when a voltage on a second data pin of the USB connector is equal to or greater than 0.8 to 2.0 Volts (V), and is false otherwise. When the condition is true, a first signal is sent on a control circuit output indicating indicate that the PD is connected to a dedicated charging port (DCP) of Divider 0 mode. When the condition is false, a second signal is sent on the control circuit output indicating that the PD is connected to a DCP of 1.2V short mode.

公开(公告)号：US12199694B2

公开(公告)日：2025-01-14

申请号：US18461574

申请日：2023-09-06

Applicant: Texas Instruments Incorporated

Inventor： Suzanne Mary Vining ,  Gary Chard ,  Win Naing Maung ,  Mark Alan McAdams

IPC: H04B3/54 ,  G06F13/42

Abstract: At least some aspects of the present disclosure provide for a method. In some examples, the method includes receiving 2-line data in an embedded Universal Serial Bus (eUSB) format. The method further includes encoding the 2-line data into a single signal. The single signal comprises a first symbol corresponding to a first state change of the 2-line data and a second symbol corresponding to a second state change of the 2-line data.

公开(公告)号：US20240354270A1

公开(公告)日：2024-10-24

申请号：US18760375

申请日：2024-07-01

Applicant: Texas Instruments Incorporated

Inventor： Suzanne Mary Vining ,  Win Naing Maung

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4004 ,  G06F13/4282 ,  G06F2213/0042

Abstract: An embedded USB2 (eUSB2) repeater includes an eUSB2 port having first and second terminals. The eUSB2 port facilitates two-way communication between the repeater and an application processor unit (APU) according to voltage level specifications for eUSB2. The repeater includes a USB port having first and second terminals. The USB port facilitates two-way communication between the repeater and a Universal Asynchronous Receiver Transmitter (UART) according to voltage level specifications for US. The repeater includes a multiplexer having an input coupled to receive a control signal. The multiplexer selectively establishes connections between the first and second terminals of the eUSB2 port and the first and second terminals of the USB port.

公开(公告)号：US12026521B2

公开(公告)日：2024-07-02

申请号：US17521378

申请日：2021-11-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mark Edward Wentroble ,  Anant Shankar Kamath ,  Rakesh Hariharan ,  Prajwala P ,  Suzanne Mary Vining

IPC: G06F13/00 ,  G06F1/3215 ,  G06F9/4401 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F9/4411 ,  G06F1/3215 ,  G06F13/382 ,  G06F13/4282 ,  G06F2213/0042

Abstract: A serial bus repeater includes first and second ports adapted to be coupled to respective devices. A first termination resistor network couples to the first port. A second termination resistor network couples to the second port. A squelch detect circuit couples to the first bus port and is configured to detect activity on the first bus and to generate a squelch signal responsive to detection of activity on the first port. A first state machine is configured to: determine an elapsed time during which the squelch signal indicates activity on the first port; determine that the elapsed time exceeds a first threshold; and, responsive to the determination that the elapsed time exceeds the first threshold, assert configuration signals to reconfigure the first and second termination resistor networks.

公开(公告)号：US20240103595A1

公开(公告)日：2024-03-28

申请号：US18534911

申请日：2023-12-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mustafa Ulvi Erdogan ,  Suzanne Mary Vining ,  Bharath Kumar Singareddy ,  Douglas Edward Wente

IPC: G06F1/3215 ,  G06F1/3234 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F1/3215 ,  G06F1/3253 ,  G06F13/385 ,  G06F13/4282 ,  G06F2213/0042

Abstract: High-speed data communication devices, e.g., repeaters, interfacing between a host and a peripheral operate such that high-speed components except for a host-side squelch detector are set or maintained in a deactivated state during an idle period of a micro frame. In an example, a start of a micro frame is detected on a data bus during a first time period. In a second time period after the first time period, the high-speed communication device determines whether at least one data packet is contained in the micro frame. When it is determined during the second time period that no data packet is contained in the micro frame, active components, except a squelch detector, are controlled to be inactive during a third time period after the second time period.