公开(公告)号：US10121891B2

公开(公告)日：2018-11-06

申请号：US15364971

申请日：2016-11-30

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar ,  Henry Litzmann Edwards

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66 ,  H01L27/092

Abstract: RESURF-based dual-gate p-n bimodal conduction laterally diffused metal oxide semiconductors (LDMOS). In an illustrative embodiment, a p-type source is electrically coupled to an n-type drain. A p-type drain is electrically coupled to an n-type source. An n-type layer serves as an n-type conduction channel between the n-type drain and the n-type source. A p-type top layer is disposed at the surface of the substrate of said semiconductor device and is disposed above and adjacent to the n-type layer. The p-type top layer serves as a p-type conduction channel between the p-type source and the p-type drain. An n-gate controls current flow in the n-type conduction channel, and a p-gate controls current flow in the p-type conduction channel.

公开(公告)号：US09985028B2

公开(公告)日：2018-05-29

申请号：US15491179

申请日：2017-04-19

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar ,  Scott G. Balster

IPC: H01L21/761 ,  H01L27/092 ,  H01L29/66 ,  H01L21/266 ,  H01L21/762 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L27/0922 ,  H01L21/266 ,  H01L21/76224 ,  H01L27/092 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7816

Abstract: A multi-finger lateral high voltage transistors (MFLHVT) includes a substrate doped a first dopant type, a well doped a second dopant type, and a buried drift layer (BDL) doped first type having a diluted BDL portion (DBDL) including dilution stripes. A semiconductor surface doped the second type is on the BDL. Dielectric isolation regions have gaps defining a first active area in a first gap region (first MOAT) and a second active area in a second gap region (second MOAT). A drain includes drain fingers in the second MOAT interdigitated with source fingers in the first MOAT each doped second type. The DBDL is within a fingertip drift region associated drain fingertips and/or source fingertips between the first and second MOAT. A gate stack is on the semiconductor surface between source and drain. The dilution stripes have stripe widths that increase monotonically with a drift length at their respective positions.

公开(公告)号：US20170264289A1

公开(公告)日：2017-09-14

申请号：US15067928

申请日：2016-03-11

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar ,  Philip L. Hower ,  Salvatore Giombanco ,  Filippo Marino ,  Seetharaman Sridhar

IPC: H03K17/687 ,  H01L29/06 ,  H03K19/0185 ,  H01L27/092

CPC classification number: H03K19/018521 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1033 ,  H01L29/7816 ,  H01L29/7831 ,  H03K17/122

Abstract: An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.

公开(公告)号：US09653577B2

公开(公告)日：2017-05-16

申请号：US15220910

申请日：2016-07-27

Applicant: Texas Instruments Incorporated

Inventor： Yongxi Zhang ,  Sameer P. Pendharkar ,  Scott G. Balster

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L27/092 ,  H01L21/762 ,  H01L29/06 ,  H01L21/266

CPC classification number: H01L27/0922 ,  H01L21/266 ,  H01L21/76224 ,  H01L27/092 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7816

Abstract: A multi-finger lateral high voltage transistors (MFLHVT) includes a substrate doped a first dopant type, a well doped a second dopant type, and a buried drift layer (BDL) doped first type having a diluted BDL portion (DBDL) including dilution stripes. A semiconductor surface doped the second type is on the BDL. Dielectric isolation regions have gaps defining a first active area in a first gap region (first MOAT) and a second active area in a second gap region (second MOAT). A drain includes drain fingers in the second MOAT interdigitated with source fingers in the first MOAT each doped second type. The DBDL is within a fingertip drift region associated drain fingertips and/or source fingertips between the first and second MOAT. A gate stack is on the semiconductor surface between source and drain. The dilution stripes have stripe widths that increase monotonically with a drift length at their respective positions.

公开(公告)号：US08749024B2

公开(公告)日：2014-06-10

申请号：US14073611

申请日：2013-11-06

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Marie Denison ,  Yongxi Zhang

IPC: H01L27/082

CPC classification number: H01L27/082 ,  H01L21/8222 ,  H01L27/0259 ,  H01L27/0823 ,  H01L29/735

Abstract: An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed.

Abstract translation: 公开了一种包含串联连接的两个双极晶体管的叠层双极晶体管的集成电路。 每个双极晶体管包括击穿诱导特征。 击穿诱发特征相对于彼此具有反射对称性。 还公开了一种用于形成集成电路的方法，该集成电路包括具有串联连接的两个双极晶体管和具有反射对称性的击穿诱发特征的堆叠双极晶体管。

公开(公告)号：US20140061859A1

公开(公告)日：2014-03-06

申请号：US14073611

申请日：2013-11-06

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Marie Denison ,  Yongxi Zhang

IPC: H01L27/082

CPC classification number: H01L27/082 ,  H01L21/8222 ,  H01L27/0259 ,  H01L27/0823 ,  H01L29/735

Abstract: An integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series is disclosed. Each bipolar transistor includes a breakdown inducing feature. The breakdown inducing features have reflection symmetry with respect to each other. A process for forming an integrated circuit containing a stacked bipolar transistor which includes two bipolar transistors connected in series, with breakdown inducing features having reflection symmetry, is also disclosed.

Abstract translation: 公开了一种包含串联连接的两个双极晶体管的叠层双极晶体管的集成电路。 每个双极晶体管包括击穿诱导特征。 击穿诱发特征相对于彼此具有反射对称性。 还公开了一种用于形成集成电路的方法，该集成电路包括具有串联连接的两个双极晶体管和具有反射对称性的击穿诱发特征的堆叠双极晶体管。