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    Inner Spacer Formation in Multi-Gate Transistors
    21.
    发明申请
    Inner Spacer Formation in Multi-Gate Transistors 有权

    公开(公告)号：US20210391447A1

    公开(公告)日：2021-12-16

    申请号：US17458087

    申请日：2021-08-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Han-Yu Lin ,  Chansyun David Yang ,  Tze-Chung Lin ,  Fang-Wei Lee ,  Fo-Ju Lin ,  Li-Te Lin ,  Pinyen Lin

    IPC: H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L29/06

    Abstract: A method of fabricating a semiconductor device includes forming a channel member suspended above a substrate, depositing a dielectric material layer wrapping around the channel member, performing an oxidation treatment to a surface portion of the dielectric material layer, selectively etching the surface portion of the dielectric material layer to expose sidewalls of the channel member, performing a nitridation treatment to remaining portions of the dielectric material layer and the exposed sidewalls of the channel member, thereby forming a nitride passivation layer partially wrapping around the channel member. The method also includes repeating the steps of performing the oxidation treatment and selectively etching until top and bottom surfaces of the channel member are exposed, removing the nitride passivation layer from the channel member, and forming a gate structure wrapping around the channel member.

    TRANSISTOR SPACER STRUCTURES
    24.
    发明申请
    TRANSISTOR SPACER STRUCTURES 有权

    公开(公告)号：US20210098598A1

    公开(公告)日：2021-04-01

    申请号：US16690441

    申请日：2019-11-21

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chansyun David Yang

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/02

    Abstract: The present disclosure describes a method for forming gate spacer structures with air-gaps to reduce the parasitic capacitance between the transistor's gate structures and the source/drain contacts. In some embodiments, the method includes forming a gate structure on a substrate and a spacer stack on sidewall surfaces of the gate structure—where the spacer stack comprises an inner spacer layer in contact with the gate structure, a sacrificial spacer layer on the inner spacer layer, and an outer spacer layer on the sacrificial spacer layer. The method further includes removing the sacrificial spacer layer to form an opening between the inner and outer spacer layers, depositing a polymer material on top surfaces of the inner and outer spacer layers, etching top sidewall surfaces of the inner and outer spacer layers to form a tapered top portion, and depositing a seal material.

    Inner Spacer Formation in Multi-Gate Transistors
    28.
    发明申请
    Inner Spacer Formation in Multi-Gate Transistors 有权

    公开(公告)号：US20230118700A1

    公开(公告)日：2023-04-20

    申请号：US18066354

    申请日：2022-12-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Han-Yu Lin ,  Chansyun David Yang ,  Tze-Chung Lin ,  Fang-Wei Lee ,  Fo-Ju Lin ,  Li-Te Lin ,  Pinyen Lin

    IPC: H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L29/06

    Abstract: A method for forming a semiconductor structure includes forming a fin on a semiconductor substrate. The fin includes channel layers and sacrificial layers stacked one on top of the other in an alternating fashion. The method also includes removing a portion of the fin to form a first opening and expose vertical sidewalls of the channel layers and the sacrificial layers, epitaxially growing a source/drain feature in the first opening from the exposed vertical sidewalls of the channel layers and the sacrificial layers, removing another portion of the fin to form a second opening to expose a vertical sidewall of the source/drain feature, depositing a dielectric layer in the second opening to cover the exposed vertical sidewall of the source/drain feature, and replacing the sacrificial layers with a metal gate structure in the second opening. The dielectric layer separates the source/drain feature from contacting the metal gate structure.

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