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公开(公告)号:US20200020363A1
公开(公告)日:2020-01-16
申请号:US16582029
申请日:2019-09-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Fu-An Wu , Cheng Hung Lee , Chen-Lin Yang , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yu-Hao Hsu
IPC: G11C5/14 , H03K17/22 , H03K17/687
Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.
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公开(公告)号:US20190005990A1
公开(公告)日:2019-01-03
申请号:US15902118
申请日:2018-02-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Fu-An Wu , Cheng Hung Lee , Chen-Lin Yang , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yu-Hao Hsu
IPC: G11C5/14 , H03K17/687
Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.
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公开(公告)号:US09979399B2
公开(公告)日:2018-05-22
申请号:US15073948
申请日:2016-03-18
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Chien-Yuan Chen , Cheng Hung Lee , Hung-Jen Liao , Hau-Tai Shieh , Che-Ju Yeh
IPC: H03L5/00 , H03K19/0185
CPC classification number: H03K19/018521
Abstract: A circuit is disclosed. The circuit includes eight MOD transistors and a capacitor, the first MOS transistor having a source coupled to a first predetermined supply voltage (VDDM), a second MOS transistor having a source coupled to a first predetermined supply voltage VDDM, a third MOS transistor having a source coupled to a drain of the first MOS transistor, a fourth MOS transistor having a source coupled to a drain of the second MOS transistor, a fifth MOS transistor having a source coupled to a drain of the third MOS transistor and a gate of the second MOS transistor, and a gate coupled to a gate of the third MOS transistor and an input node, and a drain coupled to ground, a sixth MOS transistor having a source coupled to a drain of the fourth MOS transistor and a gate of the first MOS transistor and an output node.
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24.
公开(公告)号:US20140269115A1
公开(公告)日:2014-09-18
申请号:US13873526
申请日:2013-04-30
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.
Inventor: Chung-Hsien Hua , Yu-Hao Hsu , Chen-Lin Yang , Cheng Hung Lee
IPC: G11C7/12
CPC classification number: G11C7/12 , G11C7/1078 , G11C7/1096 , G11C8/08 , G11C11/419 , G11C11/5628
Abstract: An integrated driver system is disclosed. The driver system includes decoding logic and a driver portion. The decoding logic is configured to receive select signals and data signals. The driver portion is configured to generate driver signals according to the decoded signals.
Abstract translation: 公开了一种集成驱动器系统。 驱动器系统包括解码逻辑和驱动器部分。 解码逻辑被配置为接收选择信号和数据信号。 驱动器部分被配置为根据解码的信号产生驱动器信号。
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公开(公告)号:US11728789B2
公开(公告)日:2023-08-15
申请号:US17406273
申请日:2021-08-19
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chia-Chen Kuo , Yangsyu Lin , Yu-Hao Hsu , Cheng Hung Lee , Hung-Jen Liao , Jonathan Tsung-Yung Chang
IPC: H03K3/012
CPC classification number: H03K3/012
Abstract: The present disclosure describes an example circuit for selecting a voltage supply. The circuit includes a first control switch, a first voltage supply switch, a second control switch, and a second voltage supply switch. The first control switch is configured to receive a control signal and a first voltage supply. The first voltage supply switch is electrically coupled to the first control switch and is configured to receive a second voltage supply. The second voltage supply switch is electrically coupled to the second control switch and configured to receive the first voltage supply. The first and second voltage supply switches are configured to selectively output the first and second voltage supplies based on the control signal.
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公开(公告)号:US10304500B2
公开(公告)日:2019-05-28
申请号:US15902118
申请日:2018-02-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Fu-An Wu , Cheng Hung Lee , Chen-Lin Yang , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yu-Hao Hsu
IPC: G11C5/14 , H03K17/687 , H03K17/22
Abstract: An electronic device includes an internal supply rail; a plurality of first main header switches for coupling the internal supply rail to a first power supply; a plurality of second main header switches for coupling the internal supply rail to a second power supply; an auxiliary circuit including a first auxiliary header switch for coupling the internal supply rail to the first power supply and a second auxiliary header switch for coupling the internal supply rail to the second power supply; a feedback circuit, the feedback circuit tracking a status of the first and second main header switches; and a control circuit, the control circuit controlling the first main header switches, second main header switches and first and second auxiliary header switches responsive to the switch control signal and an output of the feedback circuit.
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公开(公告)号:US20170040042A1
公开(公告)日:2017-02-09
申请号:US14980287
申请日:2015-12-28
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Hektor Huang , Yangsyu Lin , Yu-Hao Hsu , Chia-En Huang , Chiting Cheng , Chen-Lin Yang , Jung-Ping Yang , Cheng Hung Lee
Abstract: A power management circuit for an electronic device is disclosed that sequentially activates and/or deactivates electronic circuits of the electronic device. The power management circuit provides a first group of one or more circuit power management signals to activate and/or deactivate a first electronic circuit from among the electronic circuits. Thereafter, the power management circuit provides a corresponding power management signal from among a second group of the one or more circuit power management signals that corresponds to a portion of the first electronic circuit that has been activated and/or deactivated by the first group of the one or more circuit power management signals to activate and/or deactivate a portion of a second electronic circuit from among the electronic circuits. The power management circuit continues to sequentially provide each of the one or more circuit power management signals in a similar manner until the electronic circuits of the electronic device have been activated and/or deactivated.
Abstract translation: 公开了一种用于电子设备的电源管理电路,其顺序地激活和/或去激活电子设备的电子电路。 功率管理电路提供第一组一个或多个电路功率管理信号以激活和/或去激活来自电子电路之间的第一电子电路。 此后,电源管理电路从一个或多个电路电源管理信号的第二组中提供相应的功率管理信号,其对应于已经被第一组的第一组激活和/或去激活的第一电子电路的一部分 一个或多个电路功率管理信号,用于激活和/或去激活来自电子电路的第二电子电路的一部分。 功率管理电路以类似的方式继续顺序提供一个或多个电路功率管理信号中的每一个,直到电子设备的电子电路已经被激活和/或去激活为止。
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28.
公开(公告)号:US09218262B2
公开(公告)日:2015-12-22
申请号:US13972082
申请日:2013-08-21
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Fu-An Wu , Jung-Ping Yang , Chia-En Huang , Cheng Hung Lee
CPC classification number: G06F11/25 , G11C29/00 , G11C29/808 , G11C29/848
Abstract: A memory chip comprises a main memory array having a plurality of memory columns, a redundancy memory column associated with the main memory array, and a hit logic circuitry configured to generate a plurality of hit logic signals by a plurality of hit logic units in the hit logic circuitry to enable dynamic replacement of a defective memory cell in one of the memory columns for dynamic replacement by the redundancy memory column when the memory array is in operation.
Abstract translation: 存储器芯片包括具有多个存储器列的主存储器阵列,与主存储器阵列相关联的冗余存储器列,以及命中逻辑电路,其被配置为通过命中中的多个命中逻辑单元产生多个命中逻辑信号 逻辑电路,用于在存储器列之一中动态替换存储器列之一中的有缺陷的存储器单元,以便在存储器阵列运行时由冗余存储器列进行动态替换。
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