公开(公告)号：US11508615B2

公开(公告)日：2022-11-22

申请号：US16943996

申请日：2020-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L23/532

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a conductive structure disposed over the device, and the conductive structure includes a sidewall having a first portion and a second portion. The semiconductor device structure further includes a first spacer layer including a third portion and a fourth portion, the third portion surrounds the first portion of the sidewall, and the fourth portion is disposed on the conductive structure. The semiconductor device structure further includes a first dielectric material surrounding the third portion, and an air gap is formed between the first dielectric material and the third portion of the first spacer layer. The first dielectric material includes a first material different than a second material of the first spacer layer, and the first dielectric material is substantially coplanar with the fourth portion of the first spacer layer.

公开(公告)号：US11387233B2

公开(公告)日：2022-07-12

申请号：US16915930

申请日：2020-06-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Huan-Chieh Su ,  Chun-Yuan Chen ,  Pei-Yu Wang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L29/08 ,  H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a source region, a drain region, and a gate electrode layer disposed between the source region and the drain region. The gate electrode layer includes a first surface facing the source region, and the first surface includes an edge portion having a first height. The gate electrode layer further includes a second surface opposite the first surface and facing the drain region. The second surface includes an edge portion having a second height. The second height is different from the first height.

公开(公告)号：US11355601B2

公开(公告)日：2022-06-07

申请号：US17080521

申请日：2020-10-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Shi Ning Ju ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Cheng-Chi Chuang

IPC: H01L29/417 ,  H01L23/528 ,  H01L23/522 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40 ,  H01L29/06

Abstract: A semiconductor structure includes a source feature, a drain feature, one or more channel layers connecting the source feature and the drain feature, and a gate structure between the source feature and the drain feature. The gate structure engages each of the one or more channel layers. The semiconductor structure further includes a first source silicide feature over the source feature, a source contact over the first source silicide feature, a second source silicide feature under the source feature, a via under the second source silicide feature, and a power rail under the via. The first and the second source silicide features fully surround the source feature in a cross-sectional view. The power rail is a backside power rail.

公开(公告)号：US11342413B2

公开(公告)日：2022-05-24

申请号：US16944263

申请日：2020-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/06 ,  H01L23/528

Abstract: A method includes providing a structure having a substrate, a fin, source/drain (S/D) features, an isolation structure adjacent to sidewalls of the fin, one or more channel layers over a first dielectric layer and connecting the S/D features, and a gate structure engaging the one or more channel layers. The method further includes thinning down the structure from its backside until the fin is exposed and selectively etching the fin to form a trench that exposes surfaces of the S/D features, the first dielectric layer, and the isolation structure. The method further includes forming a silicide feature on the S/D features and depositing an inhibitor on the silicide feature but not on the surface of the first dielectric layer and the isolation structure, depositing a dielectric liner layer on the surfaces of the isolation structure and the first dielectric layer but not on the inhibitor, and selectively removing the inhibitor.

公开(公告)号：US11328990B2

公开(公告)日：2022-05-10

申请号：US16855690

申请日：2020-04-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L23/522 ,  H01L29/78 ,  H01L27/088 ,  H01L23/528 ,  H01L29/417 ,  H01L29/66 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/285

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first insulating layer, a first metal via passing through the first insulating layer, and a second insulating layer formed over the first insulating layer. The semiconductor device structure also includes a first metal hump surrounded by the second insulating layer and connected to the top surface of the first metal via. The first metal hump covers the portion of the first insulating layer adjacent to the first metal via. In addition, the semiconductor device structure includes a metal line formed in the second insulating layer and electrically connected to the first metal via, and a conductive liner covering the first metal hump and separating the metal line from the second insulating layer and the first metal hump.

公开(公告)号：US11309212B2

公开(公告)日：2022-04-19

申请号：US16944018

申请日：2020-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first conductive structure disposed over the device, and the first conductive structure includes a first sidewall having a first portion and a second portion. The semiconductor device structure further includes a first spacer layer disposed on the first portion, a second conductive structure disposed adjacent the first conductive structure, and the second conductive structure includes a second sidewall having a third portion and a fourth portion. The semiconductor device structure further includes a second spacer layer disposed on the third portion, and an air gap is formed between the first conductive structure and the second conductive structure. The second portion, the first spacer layer, the fourth portion, and the second spacer layer are exposed to the air gap.

公开(公告)号：US20220037486A1

公开(公告)日：2022-02-03

申请号：US17337962

申请日：2021-06-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L29/40

Abstract: A semiconductor structure includes a semiconductor substrate, a metallization feature over the semiconductor substrate, a first dielectric feature, a second dielectric feature, and a via contact. The metallization feature includes a first bottom corner and a second bottom corner opposite to the first bottom corner. The first dielectric feature is adjacent to the first bottom corner, and the second dielectric feature is adjacent to the second bottom corner. The metallization feature is interposed between the first dielectric feature and the second dielectric feature. In some embodiments, an included angle of the first bottom corner defined by a sidewall of first dielectric feature and a bottom surface of the metallization feature is less than 90°. The via contact is configured to connect the metallization feature to the semiconductor substrate.

公开(公告)号：US11233005B1

公开(公告)日：2022-01-25

申请号：US16926447

申请日：2020-07-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Huan-Chieh Su ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/417 ,  H01L23/522 ,  H01L29/78 ,  H01L29/06 ,  H01L27/088 ,  H01L23/528

Abstract: A method includes providing a fin, an isolation structure, and first and second source/drain (S/D) features over the fin; forming an etch mask covering a first portion and exposing a second portion of the fin; removing the second portion of the fin, resulting in a first trench; filling the first trench with a first dielectric feature; removing the etch mask; and applying etching process(es) to remove the first portion of the fin and to partially recess the first S/D feature. The etching process(es) includes an isotropic etching tuned selective to materials of the first S/D feature and not materials of the isolation structure and the first dielectric feature, resulting in a second trench under the first S/D feature and having a gap between a bottom surface of the first S/D feature and a top surface of the isolation structure. The method further includes forming a via in the second trench.

公开(公告)号：US20210391438A1

公开(公告)日：2021-12-16

申请号：US16901749

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Chuan Chiu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Yu-Ming Lin

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/417 ,  H01L23/532 ,  H01L21/8234

Abstract: The present disclosure provides a semiconductor device structure that includes: a fin active region extruded above a semiconductor substrate; a gate stack disposed on the fin active region, wherein the gate stack includes a gate dielectric layer and a gate electrode; source/drain (S/D) features formed on the fin active region and interposed by the gate stack; and a conductive feature electrically connected to one of the gate electrode and the S/D features. The conductive feature includes a bottom metal feature of a first metal; a top metal feature of a second metal over the bottom metal feature, wherein the second metal is different from the first metal in composition; a barrier layer surrounding both the top metal feature and the bottom metal feature; and a liner surrounding both the top metal feature and separating the top metal feature from the bottom metal feature and the barrier layer.

公开(公告)号：US20210375761A1

公开(公告)日：2021-12-02

申请号：US17126509

申请日：2020-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Wen Chang ,  Yi-Hsun Chiu ,  Cheng-Chi Chuang ,  Ching-Wei Tsai ,  Wei-Cheng Lin ,  Shih-Wei Peng ,  Jiann-Tyng Tzeng

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L23/00

Abstract: In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.