公开(公告)号：US11335681B2

公开(公告)日：2022-05-17

申请号：US16919063

申请日：2020-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/49

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate structure, spacers and source and drain regions is described. The substrate has a plurality of fins and a plurality of insulators disposed between the fins. The source and drain regions are disposed on two opposite sides of the at least one gate structure. The gate structure is disposed over the plurality of fins and disposed on the plurality of insulators. The gate structure includes a stacked strip disposed on the substrate and a gate electrode stack disposed on the stacked strip. The spacers are disposed on opposite sidewalls of the gate structure, and the gate electrode stack contacts sidewalls of the opposite spacers.

公开(公告)号：US20220122972A1

公开(公告)日：2022-04-21

申请号：US17567476

申请日：2022-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Yun-Ting Chou ,  Chih-Han Lin ,  Jr-Jung Lin

IPC: H01L27/092 ,  H01L21/311 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66

Abstract: An embodiment device includes a first source/drain region over a semiconductor substrate and a dummy fin adjacent the first source/drain region. The dummy fin comprising: a first portion comprising a first film and a second portion over the first portion, wherein the second portion comprises: a second film; and a third film. The third film is between the first film and the second film, and the third film is made of a different material than the first film and the second film. A width of the second portion is less than a width of the first portion. The device further comprises a gate stack along sidewalls of the dummy fin.

公开(公告)号：US20220028997A1

公开(公告)日：2022-01-27

申请号：US17244430

申请日：2021-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Liang Lu ,  Chang-Yin Chen ,  Chih-Han Lin ,  Chia-Yang Liao

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure with a fin top surface disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, a gate structure disposed on the fin top surface, and a gate spacer with first and second spacer portions disposed between the gate structure and the S/D region. The first spacer portion extends above the fin top surface and is disposed along a sidewall of the gate structure. The second spacer portion extends below the fin top surface and is disposed along a sidewall of the S/D region.

公开(公告)号：US20210359109A1

公开(公告)日：2021-11-18

申请号：US17101291

申请日：2020-11-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Ping Chen ,  Kuei-Yu Kao ,  Shih-Yao Lin ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: A device includes a fin protruding from a semiconductor substrate; a gate stack over and along a sidewall of the fin; a gate spacer along a sidewall of the gate stack and along the sidewall of the fin; an epitaxial source/drain region in the fin and adjacent the gate spacer; and a corner spacer between the gate stack and the gate spacer, wherein the corner spacer extends along the sidewall of the fin, wherein a first region between the gate stack and the sidewall of the fin is free of the corner spacer, wherein a second region between the gate stack and the gate spacer is free of the corner spacer.

公开(公告)号：US11145510B2

公开(公告)日：2021-10-12

申请号：US16666218

申请日：2019-10-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Che-Cheng Chang ,  Po-Chi Wu ,  Chih-Han Lin ,  Horng-Huei Tseng

IPC: H01L27/12 ,  H01L29/06 ,  H01L21/225 ,  H01L29/78 ,  H01L29/66 ,  H01L29/36 ,  H01L21/84 ,  H01L21/8234 ,  H01L27/088

Abstract: A semiconductor device includes a substrate, a FinFET, and an insulating structure. The FinFET includes a fin, a gate electrode, and a gate dielectric layer. The fin is over the substrate. The gate electrode is over the fin. The gate dielectric layer is between the gate electrode and the fin. The insulating structure is over the substrate, adjacent the fin, and has a top surface lower than a top surface of the fin. The top surface of the insulating structure has opposite first and second edge portions and an intermediate portion between the first and second edge portions. The first edge portion of the top surface of the insulating structure is lower than the intermediate portion of the top surface of the insulating structure.

公开(公告)号：US20210313216A1

公开(公告)日：2021-10-07

申请号：US17349741

申请日：2021-06-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/764 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor device includes a first gate structure disposed over a substrate. The first gate structure extends in a first direction. A second gate structure is disposed over the substrate. The second gate structure extends in the first direction. A dielectric material is disposed between the first gate structure and the second gate structure. An air gap is disposed within the dielectric material.

公开(公告)号：US20210257359A1

公开(公告)日：2021-08-19

申请号：US16899268

申请日：2020-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Sheng Lai ,  Wei-Chung Sun ,  Li-Ting Chen ,  Kuei-Yu Kao ,  Chih-Han Lin

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: A device includes a plurality of fin structures that each protrude vertically upwards out of a substrate and each extend in a first direction in a top view. A gate structure is disposed over the fin structures. The gate structure extends in a second direction in the top view. The second direction is different from the first direction. The fin structures have a fin pitch equal to a sum of: a dimension of one of the fin structures in the second direction and a distance between an adjacent pair of the fin structures in the second direction. An end segment of the gate structure extends beyond an edge of a closest one of the fin structures in the second direction. The end segment has a tapered profile in the top view or is at least 4 times as long as the fin pitch in the second direction.

公开(公告)号：US20210242206A1

公开(公告)日：2021-08-05

申请号：US16837563

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Yun-Ting Chou ,  Chih-Han Lin ,  Jr-Jung Lin

IPC: H01L27/092 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/66

Abstract: An embodiment device includes a first source/drain region over a semiconductor substrate and a dummy fin adjacent the first source/drain region. The dummy fin comprising: a first portion comprising a first film and a second portion over the first portion, wherein the second portion comprises: a second film; and a third film. The third film is between the first film and the second film, and the third film is made of a different material than the first film and the second film. A width of the second portion-is less than a width of the first portion. The device further comprises a gate stack along sidewalls of the dummy fin.

公开(公告)号：US20210125859A1

公开(公告)日：2021-04-29

申请号：US16870389

申请日：2020-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin

IPC: H01L21/768 ,  H01L21/306 ,  H01L21/3065

Abstract: A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.

公开(公告)号：US20210125833A1

公开(公告)日：2021-04-29

申请号：US16811079

申请日：2020-03-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate over the fin; reducing a thickness of a lower portion of the dummy gate proximate to the isolation regions, where after reducing the thickness, a distance between opposing sidewalls of the lower portion of the dummy gate decreases as the dummy gate extends toward the isolation regions; after reducing the thickness, forming a gate fill material along at least the opposing sidewalls of the lower portion of the dummy gate; forming gate spacers along sidewalls of the dummy gate and along sidewalls of the gate fill material; and replacing the dummy gate with a metal gate.