公开(公告)号：US11114549B2

公开(公告)日：2021-09-07

申请号：US15909800

申请日：2018-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ryan Chia-Jen Chen ,  Ming-Ching Chang ,  Yi-Chun Chen ,  Yu-Hsien Lin ,  Li-Wei Yin ,  Tzu-Wen Pan ,  Cheng-Chung Chang ,  Shao-Hua Hsu

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/84 ,  H01L27/12

Abstract: Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin and a second fin on a substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes a liner on a first sidewall of the first fin, and an insulating fill material on a sidewall of the liner and on a second sidewall of the first fin. The liner is further on a surface of the first fin between the first sidewall of the first fin and the second sidewall of the first fin.

公开(公告)号：US20210273072A1

公开(公告)日：2021-09-02

申请号：US16889427

申请日：2020-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08

Abstract: Semiconductor devices and methods of forming are described herein. The methods include depositing a dummy gate material layer over a fin etched into a substrate. A gate mask is then formed over the dummy gate material layer in a channel region of the fin. A dummy gate electrode is etched into the dummy gate material using the gate mask. A top spacer is then deposited over the gate mask and along sidewalls of a top portion of the dummy gate electrode. An opening is then etched through the remainder of the dummy gate material and through the fin. A bottom spacer is then formed along a sidewall of the opening and separates a bottom portion of the dummy gate electrode from the opening. A source/drain region is then formed in the opening and the dummy gate electrode is replaced with a metal gate stack.

公开(公告)号：US20210193528A1

公开(公告)日：2021-06-24

申请号：US17195189

申请日：2021-03-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Yi Tsai ,  Yi-Hsuan Hsiao ,  Shu-Yuan Ku ,  Ryan Chia-Jen Chen ,  Ming-Ching Chang

IPC: H01L21/8234 ,  H01L27/088

Abstract: Metal gate cutting techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes receiving an integrated circuit (IC) device structure that includes a substrate, one or more fins disposed over the substrate, a plurality of gate structures disposed over the fins, a dielectric layer disposed between and adjacent to the gate structures, and a patterning layer disposed over the gate structures. The gate structures traverses the fins and includes first and second gate structures. The method further includes: forming an opening in the patterning layer to expose a portion of the first gate structure, a portion of the second gate structure, and a portion of the dielectric layer; and removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.

公开(公告)号：US20210083087A1

公开(公告)日：2021-03-18

申请号：US17107589

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jr-Jung Lin ,  Chih-Han Lin ,  Jin-Aun Ng ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/78 ,  H01L21/283 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8238

Abstract: Embodiments relate to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first gate electrode; and a second dielectric material adjacent to the other 3 sides of the first gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first gate electrode.

公开(公告)号：US10943828B2

公开(公告)日：2021-03-09

申请号：US16665252

申请日：2019-10-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Yi Tsai ,  Yi-Hsuan Hsiao ,  Shu-Yuan Ku ,  Ryan Chia-Jen Chen ,  Ming-Ching Chang

IPC: H01L21/8234 ,  H01L27/088

Abstract: Metal gate cutting techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes receiving an integrated circuit (IC) device structure that includes a substrate, one or more fins disposed over the substrate, a plurality of gate structures disposed over the fins, a dielectric layer disposed between and adjacent to the gate structures, and a patterning layer disposed over the gate structures. The gate structures traverses the fins and includes first and second gate structures. The method further includes: forming an opening in the patterning layer to expose a portion of the first gate structure, a portion of the second gate structure, and a portion of the dielectric layer; and removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.

公开(公告)号：US10510894B2

公开(公告)日：2019-12-17

申请号：US15941137

申请日：2018-03-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Yun Chang ,  Ming-Ching Chang ,  Shu-Yuan Ku

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/306 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/092

Abstract: A first FinFET device includes first fin structures that extend in a first direction in a top view. A second FinFET device includes second fin structures that extend in the first direction in the top view. The first FinFET device and the second FinFET device are different types of FinFET devices. A plurality of gate structures extend in a second direction in the top view. The second direction is different from the first direction. Each of the gate structures partially wraps around the first fin structures and the second fin structures. A dielectric structure is disposed between the first FinFET device and the second FinFET device. The dielectric structure cuts each of the gate structures into a first segment for the first FinFET device and a second segment for the second FinFET device. The dielectric structure is located closer to the first FinFET device than to the second FinFET device.

公开(公告)号：US20190164839A1

公开(公告)日：2019-05-30

申请号：US15938812

申请日：2018-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Yi Tsai ,  Yi-Hsuan Hsiao ,  Shu-Yuan Ku ,  Ryan Chia-Jen Chen ,  Ming-Ching Chang

IPC: H01L21/8234 ,  H01L27/088

Abstract: Metal gate cutting techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes receiving an integrated circuit (IC) device structure that includes a substrate, one or more fins disposed over the substrate, a plurality of gate structures disposed over the fins, a dielectric layer disposed between and adjacent to the gate structures, and a patterning layer disposed over the gate structures. The gate structures traverses the fins and includes first and second gate structures. The method further includes: forming an opening in the patterning layer to expose a portion of the first gate structure, a portion of the second gate structure, and a portion of the dielectric layer; and removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.

公开(公告)号：US20190088650A1

公开(公告)日：2019-03-21

申请号：US16195258

申请日：2018-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Yi Tsai ,  Chun-Liang Lai ,  Shu-Yuan Ku ,  Ryan Chia-Jen Chen ,  Ming-Ching Chang

IPC: H01L27/088 ,  H01L27/02 ,  H01L29/423 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/3105 ,  H01L21/027

Abstract: A method includes providing a structure having a substrate, semiconductor fins, and an isolation structure between adjacent semiconductor fins; forming a first gate structure engaging the semiconductor fins; depositing an inter-layer dielectric layer over the semiconductor fins and the first gate structure; removing the first gate structure, resulting in a first trench; depositing a second gate structure into the first trench, wherein the second gate structure includes a dielectric layer and a conductive layer; forming one or more mask layers over the second gate structure; patterning the one or more mask layers to have an opening exposing a portion of the second gate structure between two adjacent semiconductor fins; and etching the second gate structure through the opening to produce a second trench having tapered sidewalls, wherein the second trench is wider at top than at bottom.

公开(公告)号：US20190067277A1

公开(公告)日：2019-02-28

申请号：US15904835

申请日：2018-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Yi Tsai ,  Chun-Liang Lai ,  Shu-Yuan Ku ,  Ryan Chia-Jen Chen ,  Ming-Ching Chang

IPC: H01L27/088 ,  H01L27/02 ,  H01L29/423 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/3213 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, first and second fins protruding out of the substrate, and first and second high-k metal gates (HK MG) disposed over the first and second fins, respectively. From a top view, the first and second fins are arranged lengthwise along a first direction, the first and second HK MG are arranged lengthwise along a second direction generally perpendicular to the first direction, and the first and second HK MG are aligned along the second direction. In a cross-sectional view cut along the second direction, the first HK MG has a first sidewall that is slanted from top to bottom towards the second HK MG, and the second HK MG has a second sidewall that is slanted from top to bottom towards the first HK MG. Methods for producing the semiconductor device are also disclosed.

公开(公告)号：US20240194534A1

公开(公告)日：2024-06-13

申请号：US18587122

申请日：2024-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Yi Tsai ,  Yi-Hsuan Hsiao ,  Shu-Yuan Ku ,  Ryan Chia-Jen Chen ,  Ming-Ching Chang

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823437 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886

Abstract: Metal gate cutting techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes receiving an integrated circuit (IC) device structure that includes a substrate, one or more fins disposed over the substrate, a plurality of gate structures disposed over the fins, a dielectric layer disposed between and adjacent to the gate structures, and a patterning layer disposed over the gate structures. The gate structures traverses the fins and includes first and second gate structures. The method further includes: forming an opening in the patterning layer to expose a portion of the first gate structure, a portion of the second gate structure, and a portion of the dielectric layer; and removing the exposed portion of the first gate structure, the exposed portion of the second gate structure, and the exposed portion of the dielectric layer.