公开(公告)号：US20220181217A1

公开(公告)日：2022-06-09

申请号：US17652712

申请日：2022-02-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Chun Chen ,  Ryan Chia-Jen Chen ,  Shu-Yuan Ku ,  Ya-Yi Tsai ,  I-Wei Yang

IPC分类号： H01L21/8238 ,  H01L27/092

摘要： An anchored cut-metal gate (CMG) plug, a semiconductor device including the anchored CMG plug and methods of forming the semiconductor device are disclosed herein. The method includes performing a series of etching processes to form a trench through a metal gate electrode, through an isolation region, and into a semiconductor substrate. The trench cuts-through and separates the metal gate electrode into a first metal gate and a second metal gate and forms a recess in the semiconductor substrate. Once the trench has been formed, a dielectric plug material is deposited into the trench to form a CMG plug that is anchored within the recess of the semiconductor substrate and separates the first and second metal gates. As such, the anchored CMG plug provides high levels of resistance to reduce leakage current within the semiconductor device during operation and allowing for improved V-trigger performance of the semiconductor device.

公开(公告)号：US12112990B2

公开(公告)日：2024-10-08

申请号：US18301772

申请日：2023-04-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Chun Chen ,  Ya-Yi Tsai ,  I-Wei Yang ,  Ryan Chia-Jen Chen ,  Shu-Yuan Ku

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/823828 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924

摘要： An anchored cut-metal gate (CMG) plug, a semiconductor device including the anchored CMG plug and methods of forming the semiconductor device are disclosed herein. The method includes performing a series of etching processes to form a trench through a metal gate electrode, through an isolation region, and into a semiconductor substrate. The trench cuts-through and separates the metal gate electrode into a first metal gate and a second metal gate and forms a recess in the semiconductor substrate. Once the trench has been formed, a dielectric plug material is deposited into the trench to form a CMG plug that is anchored within the recess of the semiconductor substrate and separates the first and second metal gates. As such, the anchored CMG plug provides high levels of resistance to reduce leakage current within the semiconductor device during operation and allowing for improved V-trigger performance of the semiconductor device.

公开(公告)号：US12027608B2

公开(公告)日：2024-07-02

申请号：US17325622

申请日：2021-05-20

申请人： DO NOT USE—Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ryan Chia-Jen Chen ,  Li-Wei Yin ,  Tzu-Wen Pan ,  Cheng-Chung Chang ,  Shao-Hua Hsu ,  Yi-Chun Chen ,  Yu-Hsien Lin ,  Ming-Ching Chang

IPC分类号： H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/78 ,  H01L21/84 ,  H01L27/12

CPC分类号： H01L29/66795 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/785 ,  H01L21/845 ,  H01L27/1211

摘要： Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin and a second fin on a substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes a liner on a first sidewall of the first fin, and an insulating fill material on a sidewall of the liner and on a second sidewall of the first fin. The liner is further on a surface of the first fin between the first sidewall of the first fin and the second sidewall of the first fin.

公开(公告)号：US12015070B2

公开(公告)日：2024-06-18

申请号：US17814175

申请日：2022-07-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Chun Chen ,  Tsung Fan Yin ,  Li-Te Hsu ,  Ying Ting Hsia ,  Yi-Wei Chiu

IPC分类号： H01L21/00 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： A method of forming a gate structure includes forming an opening through an insulating layer and forming a first work function metal layer in the opening. The method also includes recessing the first work function metal layer into the opening to form a recessed first work function metal layer, and forming a second work function metal layer in the opening and over the first work function metal layer. The second work function metal layer lines and overhangs the recessed first work function metal layer.

公开(公告)号：US20240113112A1

公开(公告)日：2024-04-04

申请号：US18526062

申请日：2023-12-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ryan Chia-Jen Chen ,  Cheng-Chung Chang ,  Shao-Hua Hsu ,  Yu-Hsien Lin ,  Ming-Ching Chang ,  Li-Wei Yin ,  Tzu-Wen Pan ,  Yi-Chun Chen

IPC分类号： H01L27/088 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L27/0886 ,  H01L21/3065 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/7842 ,  H01L21/3212

摘要： Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

公开(公告)号：US20230253263A1

公开(公告)日：2023-08-10

申请号：US18301772

申请日：2023-04-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Chun Chen ,  Ya-Yi Tsai ,  I-Wei Yang ,  Ryan Chia-Jen Chen ,  Shu-Yuan Ku

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/823828 ,  H01L21/823878 ,  H01L21/823821 ,  H01L27/0924

摘要： An anchored cut-metal gate (CMG) plug, a semiconductor device including the anchored CMG plug and methods of forming the semiconductor device are disclosed herein. The method includes performing a series of etching processes to form a trench through a metal gate electrode, through an isolation region, and into a semiconductor substrate. The trench cuts-through and separates the metal gate electrode into a first metal gate and a second metal gate and forms a recess in the semiconductor substrate. Once the trench has been formed, a dielectric plug material is deposited into the trench to form a CMG plug that is anchored within the recess of the semiconductor substrate and separates the first and second metal gates. As such, the anchored CMG plug provides high levels of resistance to reduce leakage current within the semiconductor device during operation and allowing for improved V-trigger performance of the semiconductor device.

公开(公告)号：US11652005B2

公开(公告)日：2023-05-16

申请号：US17652712

申请日：2022-02-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Chun Chen ,  Ryan Chia-Jen Chen ,  Shu-Yuan Ku ,  Ya-Yi Tsai ,  I-Wei Yang

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/823828 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924

摘要： An anchored cut-metal gate (CMG) plug, a semiconductor device including the anchored CMG plug and methods of forming the semiconductor device are disclosed herein. The method includes performing a series of etching processes to form a trench through a metal gate electrode, through an isolation region, and into a semiconductor substrate. The trench cuts-through and separates the metal gate electrode into a first metal gate and a second metal gate and forms a recess in the semiconductor substrate. Once the trench has been formed, a dielectric plug material is deposited into the trench to form a CMG plug that is anchored within the recess of the semiconductor substrate and separates the first and second metal gates. As such, the anchored CMG plug provides high levels of resistance to reduce leakage current within the semiconductor device during operation and allowing for improved V-trigger performance of the semiconductor device.

公开(公告)号：US20240312843A1

公开(公告)日：2024-09-19

申请号：US18184024

申请日：2023-03-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tzu-Ging Lin ,  Yi-Chun Chen ,  Jih-Jse Lin

IPC分类号： H01L21/8234 ,  H01L27/088

CPC分类号： H01L21/823481 ,  H01L21/823431 ,  H01L27/0886

摘要： A method includes forming a gate stack on a semiconductor region, wherein the semiconductor region is over a bulk semiconductor substrate. The gate stack is etched to form a first trench, wherein a plurality of protruding semiconductor fins are revealed to the first trench. The plurality of protruding semiconductor fins are etched to form a plurality of second trenches extending into the bulk semiconductor substrate. The plurality of second trenches are underlying and joined to the first trench. The plurality of second trenches include a first outmost trench having a first depth, a second outmost trench, and an inner trench between the first outmost trench and the second outmost trench. The inner trench has a second depth equal to or smaller than the first depth. A fin isolation region is formed to fill the first trench and the plurality of second trenches.

公开(公告)号：US11894370B2

公开(公告)日：2024-02-06

申请号：US17818405

申请日：2022-08-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ryan Chia-Jen Chen ,  Cheng-Chung Chang ,  Shao-Hua Hsu ,  Yu-Hsien Lin ,  Ming-Ching Chang ,  Li-Wei Yin ,  Tzu-Wen Pan ,  Yi-Chun Chen

IPC分类号： H01L21/76 ,  H01L29/06 ,  H01L27/088 ,  H01L27/02 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3065 ,  H01L29/78 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/321 ,  H01L21/308 ,  H01L21/3105

CPC分类号： H01L27/0886 ,  H01L21/3065 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/7842 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/3212

摘要： Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

公开(公告)号：US20210280695A1

公开(公告)日：2021-09-09

申请号：US17325622

申请日：2021-05-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ryan Chia-Jen Chen ,  Li-Wei Yin ,  Tzu-Wen Pan ,  Cheng-Chung Chang ,  Shao-Hua Hsu ,  Yi-Chun Chen ,  Yu-Hsien Lin ,  Ming-Ching Chang

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8238 ,  H01L27/092

摘要： Methods of cutting fins, and structures formed thereby, are described. In an embodiment, a structure includes a first fin and a second fin on a substrate, and a fin cut-fill structure disposed between the first fin and the second fin. The first fin and the second fin are longitudinally aligned. The fin cut-fill structure includes a liner on a first sidewall of the first fin, and an insulating fill material on a sidewall of the liner and on a second sidewall of the first fin. The liner is further on a surface of the first fin between the first sidewall of the first fin and the second sidewall of the first fin.