公开(公告)号：US20160204118A1

公开(公告)日：2016-07-14

申请号：US14596340

申请日：2015-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Shih-Chang Liu ,  Sheng-Chieh Chen ,  Yung-Chang Chang

IPC: H01L27/115 ,  H01L29/423 ,  H01L23/528 ,  H01L21/3213 ,  H01L29/49 ,  H01L21/265 ,  H01L21/768 ,  H01L29/788 ,  H01L23/532

CPC classification number: H01L27/11521 ,  H01L21/26513 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/32139 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments of the present disclosure relate to a flash memory device. The flash memory device includes first and second individual source/drain (S/D) regions spaced apart within a semiconductor substrate. A common S/D region is arranged laterally between the first and second individual S/D regions, and is separated from the first individual S/D region by a first channel region and is separated from the second individual S/D region by a second channel region. An erase gate is arranged over the common S/D. A floating gate is disposed over the first channel region and is arranged to a first side of the erase gate. A control gate is disposed over the floating gate. A wordline is disposed over the first channel region and is spaced apart from the erase gate by the floating gate and the control gate. An upper surface of the wordline is a concave surface.

Abstract translation: 本公开的一些实施例涉及闪存设备。 闪存器件包括在半导体衬底内间隔开的第一和第二个源/漏（S / D）区域。 公共S / D区域横向地布置在第一和第二单独S / D区域之间，并且通过第一沟道区域与第一单独S / D区域分离，并且与第二个别S / D区域分开第二个 渠道区域。 擦除门被布置在公共S / D上。 浮置栅极设置在第一沟道区上方并且布置在擦除栅极的第一侧。 控制栅极设置在浮动栅极上。 字线布置在第一通道区域上方，并通过浮动栅极和控制栅极与擦除栅极间隔开。 字线的上表面是凹面。

公开(公告)号：US20160087056A1

公开(公告)日：2016-03-24

申请号：US14493538

申请日：2014-09-23

Applicant: Taiwan Semiconductor Manufacturing co., Ltd.

Inventor： Chang-Ming Wu ,  Tsung-Hsueh Yang ,  Sheng-Chieh Chen ,  Shih-Chang Liu

IPC: H01L29/423 ,  H01L27/115 ,  H01L21/28 ,  H01L29/788

CPC classification number: H01L29/42328 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/788 ,  H01L29/7881

Abstract: Some embodiments relate to a memory device with an asymmetric floating gate geometry. A control gate is arranged over a floating gate. An erase gate is arranged laterally adjacent the floating gate, and is separated from the floating gate by a tunneling dielectric layer. A sidewall spacer is arranged along a vertical sidewall of the control gate, and over an upper surface of the floating gate. A portion of the floating gate upper surface forms a “ledge,” or a sharp corner, which extends horizontally past the sidewall spacer. A sidewall of the floating gate forms a concave surface, which tapers down from the ledge towards a neck region within the floating gate. The ledge provides a faster path for tunneling of the electrons through the tunneling dielectric layer compared to a floating gate with a planar sidewall surface. The ledge consequently improves the erase speed of the memory device.

Abstract translation: 一些实施例涉及具有不对称浮动门几何形状的存储器件。 控制门布置在浮动门上。 擦除栅极横向布置在浮动栅极附近，并且通过隧道电介质层与浮动栅极分离。 侧壁间隔件沿着控制栅极的垂直侧壁并且在浮动栅极的上表面上方布置。 浮动门上表面的一部分形成水平延伸通过侧壁间隔物的“凸缘”或尖角。 浮动栅极的侧壁形成凹入表面，其从凸缘向下朝向浮动门内的颈部区域逐渐变细。 与具有平面侧壁表面的浮动栅极相比，该凸缘提供了更快的隧道隧道隧穿隧道介电层的路径。 因此，该凸起因此提高了存储器件的擦除速度。

公开(公告)号：US20150372121A1

公开(公告)日：2015-12-24

申请号：US14308872

申请日：2014-06-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chieh Chen ,  Yuan-Tai Tseng ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/788

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/7883

Abstract: A semiconductor structure of a split gate flash memory cell is provided. The semiconductor structure includes a semiconductor substrate having a source region and a drain region. Further, the semiconductor structure includes a floating gate, a word line, and an erase gate spaced over the semiconductor substrate between the source and drain regions with the floating gate arranged between the word line and the erase gate. The semiconductor structure further includes a first dielectric sidewall region disposed between the word line and the floating gate, as well as a second dielectric sidewall region disposed between the erase and floating gates. A thickness of the first dielectric sidewall region is greater than a thickness of the second dielectric sidewall region. A method of manufacturing the semiconductor structure and an integrated circuit including the semiconductor structure are also provided.

Abstract translation: 提供了分离栅闪存单元的半导体结构。 半导体结构包括具有源极区和漏极区的半导体衬底。 此外，半导体结构包括在源极和漏极区域之间间隔开半导体衬底的浮置栅极，字线和擦除栅极，其中浮置栅极布置在字线和擦除栅极之间。 半导体结构还包括设置在字线和浮置栅极之间的第一电介质侧壁区域以及设置在擦除栅极和浮置栅极之间的第二电介质侧壁区域。 第一电介质侧壁区域的厚度大于第二电介质侧壁区域的厚度。 还提供了制造半导体结构的方法和包括半导体结构的集成电路。