公开(公告)号：US20220364236A1

公开(公告)日：2022-11-17

申请号：US17812540

申请日：2022-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chang Chang ,  Meng-Yin Tsai ,  Tung-Hsiung Liu ,  Liang-Yu Yeh ,  Chun-Yi Lee ,  Kuo-Hsi Huang

IPC: C23C16/455 ,  H01L21/02 ,  C23C16/52

Abstract: In an embodiment, an apparatus includes: a susceptor including substrate pockets; a gas injector disposed over the susceptor, the gas injector having first process regions, the gas injector including a first gas mixing hub and first distribution valves connecting the first gas mixing hub to the first process regions; and a controller connected to the gas injector and the susceptor, the controller being configured to: connect a first precursor material and a carrier gas to the first gas mixing hub; mix the first precursor material and the carrier gas in the first gas mixing hub to produce a first precursor gas; rotate the susceptor to rotate a first substrate disposed in one of the substrate pockets; and while rotating the susceptor, control the first distribution valves to sequentially introduce the first precursor gas at each of the first process regions as the first substrate enters each first process region.

公开(公告)号：US20160204118A1

公开(公告)日：2016-07-14

申请号：US14596340

申请日：2015-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Shih-Chang Liu ,  Sheng-Chieh Chen ,  Yung-Chang Chang

IPC: H01L27/115 ,  H01L29/423 ,  H01L23/528 ,  H01L21/3213 ,  H01L29/49 ,  H01L21/265 ,  H01L21/768 ,  H01L29/788 ,  H01L23/532

CPC classification number: H01L27/11521 ,  H01L21/26513 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/32139 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments of the present disclosure relate to a flash memory device. The flash memory device includes first and second individual source/drain (S/D) regions spaced apart within a semiconductor substrate. A common S/D region is arranged laterally between the first and second individual S/D regions, and is separated from the first individual S/D region by a first channel region and is separated from the second individual S/D region by a second channel region. An erase gate is arranged over the common S/D. A floating gate is disposed over the first channel region and is arranged to a first side of the erase gate. A control gate is disposed over the floating gate. A wordline is disposed over the first channel region and is spaced apart from the erase gate by the floating gate and the control gate. An upper surface of the wordline is a concave surface.

Abstract translation: 本公开的一些实施例涉及闪存设备。 闪存器件包括在半导体衬底内间隔开的第一和第二个源/漏（S / D）区域。 公共S / D区域横向地布置在第一和第二单独S / D区域之间，并且通过第一沟道区域与第一单独S / D区域分离，并且与第二个别S / D区域分开第二个 渠道区域。 擦除门被布置在公共S / D上。 浮置栅极设置在第一沟道区上方并且布置在擦除栅极的第一侧。 控制栅极设置在浮动栅极上。 字线布置在第一通道区域上方，并通过浮动栅极和控制栅极与擦除栅极间隔开。 字线的上表面是凹面。

公开(公告)号：US20210376282A1

公开(公告)日：2021-12-02

申请号：US16884375

申请日：2020-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chang Chang ,  Ming Chyi Liu

IPC: H01L51/52 ,  H01L27/32

Abstract: In some embodiments, the present disclosure relates to a display device that includes a first reflector electrode and a second reflector electrode that is separated from the first reflector electrode. The display device further includes an isolation structure that overlies the first and second reflector electrodes. The isolation structure includes a first and second portion. The first portion overlies the first reflector electrode and has a first thickness. The second portion overlies the second reflector electrode, has a second thickness greater than the first thickness, and is separated from the first portion of the isolation structure. The display device also includes a first optical emitter structure and a second optical emitter structure that respectively overlie the first portion and the second portion of the isolation structure.

公开(公告)号：US20210111366A1

公开(公告)日：2021-04-15

申请号：US16601712

申请日：2019-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chang Chang ,  Ming Chyi Liu

IPC: H01L51/52 ,  H01L27/32 ,  H01L51/56

Abstract: In some embodiments, the present disclosure relates to a display device that includes an isolation structure disposed over a reflector electrode, a transparent electrode disposed over the isolation structure, an optical emitter structure disposed over the transparent electrode, and a via structure. The via structure extends from the transparent electrode at a top surface of the isolation structure to a top surface of the reflector electrode. The via structure includes a center horizontal segment that contacts the top surface of the reflector electrode, a sidewall vertical segment that contacts an inner sidewall of the isolation structure, and an upper horizontal segment that is connected to the center horizontal segment by the sidewall vertical segment. The upper horizontal segment is thicker than the center horizontal segment.

公开(公告)号：US11980046B2

公开(公告)日：2024-05-07

申请号：US16884375

申请日：2020-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chang Chang ,  Ming Chyi Liu

IPC: H10K50/818 ,  H10K50/828 ,  H10K59/122 ,  H10K59/124 ,  H10K59/12

CPC classification number: H10K50/818 ,  H10K50/828 ,  H10K59/122 ,  H10K59/124 ,  H10K59/12

Abstract: In some embodiments, the present disclosure relates to a display device that includes a first reflector electrode and a second reflector electrode that is separated from the first reflector electrode. The display device further includes an isolation structure that overlies the first and second reflector electrodes. The isolation structure includes a first and second portion. The first portion overlies the first reflector electrode and has a first thickness. The second portion overlies the second reflector electrode, has a second thickness greater than the first thickness, and is separated from the first portion of the isolation structure. The display device also includes a first optical emitter structure and a second optical emitter structure that respectively overlie the first portion and the second portion of the isolation structure.

公开(公告)号：US11333827B2

公开(公告)日：2022-05-17

申请号：US16806043

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chang Chang ,  Meng-Han Lin

IPC: G02B6/124 ,  H01L23/48 ,  G02B6/136 ,  G02B6/12

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a protective ring structure overlying a grating coupler structure. A waveguide structure is disposed within a semiconductor substrate and comprises the grating coupler structure. An interconnect structure overlies the semiconductor substrate. The interconnect structure includes a contact etch stop layer (CESL) and a conductive contact over the semiconductor substrate. The conductive contact extends through the CESL. The protective ring structure extends through the CESL and has an upper surface aligned with an upper surface of the conductive contact.

公开(公告)号：US20210271023A1

公开(公告)日：2021-09-02

申请号：US16806043

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chang Chang ,  Meng-Han Lin

IPC: G02B6/12 ,  H01L23/48

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a protective ring structure overlying a grating coupler structure. A waveguide structure is disposed within a semiconductor substrate and comprises the grating coupler structure. An interconnect structure overlies the semiconductor substrate. The interconnect structure includes a contact etch stop layer (CESL) and a conductive contact over the semiconductor substrate. The conductive contact extends through the CESL. The protective ring structure extends through the CESL and has an upper surface aligned with an upper surface of the conductive contact.

公开(公告)号：US09716097B2

公开(公告)日：2017-07-25

申请号：US14596340

申请日：2015-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Ming Wu ,  Shih-Chang Liu ,  Sheng-Chieh Chen ,  Yung-Chang Chang

IPC: H01L27/115 ,  H01L27/11521 ,  H01L29/423 ,  H01L21/265 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/788 ,  H01L27/11534

CPC classification number: H01L27/11521 ,  H01L21/26513 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/32139 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/7881 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments of the present disclosure relate to a flash memory device. The flash memory device includes first and second individual source/drain (S/D) regions spaced apart within a semiconductor substrate. A common S/D region is arranged laterally between the first and second individual S/D regions, and is separated from the first individual S/D region by a first channel region and is separated from the second individual S/D region by a second channel region. An erase gate is arranged over the common S/D. A floating gate is disposed over the first channel region and is arranged to a first side of the erase gate. A control gate is disposed over the floating gate. A wordline is disposed over the first channel region and is spaced apart from the erase gate by the floating gate and the control gate. An upper surface of the wordline is a concave surface.

公开(公告)号：US11069873B2

公开(公告)日：2021-07-20

申请号：US16601712

申请日：2019-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chang Chang ,  Ming Chyi Liu

IPC: H01L51/52 ,  H01L27/32 ,  H01L51/56

Abstract: In some embodiments, the present disclosure relates to a display device that includes an isolation structure disposed over a reflector electrode, a transparent electrode disposed over the isolation structure, an optical emitter structure disposed over the transparent electrode, and a via structure. The via structure extends from the transparent electrode at a top surface of the isolation structure to a top surface of the reflector electrode. The via structure includes a center horizontal segment that contacts the top surface of the reflector electrode, a sidewall vertical segment that contacts an inner sidewall of the isolation structure, and an upper horizontal segment that is connected to the center horizontal segment by the sidewall vertical segment. The upper horizontal segment is thicker than the center horizontal segment.

公开(公告)号：US20210098524A1

公开(公告)日：2021-04-01

申请号：US16897510

申请日：2020-06-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Chun Liu ,  Yung-Chang Chang ,  Eugene I-Chun Chen

IPC: H01L27/146

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an image sensor in which a device layer has high crystalline quality. According to some embodiments, a hard mask layer is deposited covering a substrate. A first etch is performed into the hard mask layer and the substrate to form a cavity. A second etch is performed to remove crystalline damage from the first etch and to laterally recess the substrate in the cavity so the hard mask layer overhangs the cavity. A sacrificial layer is formed lining cavity, a blanket ion implantation is performed into the substrate through the sacrificial layer, and the sacrificial layer is removed. An interlayer is epitaxially grown lining the cavity and having a top surface underlying the hard mask layer, and a device layer is epitaxially grown filling the cavity over the interlayer. A photodetector is formed in the device layer.