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公开(公告)号:US20190101821A1
公开(公告)日:2019-04-04
申请号:US16012253
申请日:2018-06-19
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Pei-Cheng HSU , Ta-Cheng LIEN , Tzu Yi WANG , Hsin-Chang LEE
IPC: G03F1/66 , H01L21/673 , G03F7/20
Abstract: A mask container for storing a mask for photolithography, includes a cover and a base having a plurality of tapered corners. The tapered corners taper outward and downward from a top major surface of the base. The cover having the tapered corners extends downward that covers the tapered corners of the base when the cover is attached to the base. The tapered corners of the cover are tapered at about the same angle as the tapered corners of the base so that a surface of the tapered corners of the cover is substantially parallel to a corresponding surface of the tapered corner of the base when the cover is attached to the base. A recess is located in the tapered corners of the cover. A biasing member and a ball-shaped member are located in the tapered corners of the base to mate with the recess when the cover is attached to the base.
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公开(公告)号:US20240192581A1
公开(公告)日:2024-06-13
申请号:US18395234
申请日:2023-12-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Pei-Cheng HSU , Ta-Cheng LIEN , Hsin-Chang LEE
IPC: G03F1/24
CPC classification number: G03F1/24
Abstract: An extreme ultraviolet mask including a substrate, a reflective multilayer stack on the substrate and a patterned absorber layer on the reflective multilayer stack is provided. The patterned absorber layer includes an alloy comprising tantalum and at least one alloying element. The at least one alloying element includes at least one transition metal element or at least one Group 14 element.
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公开(公告)号:US20230375911A1
公开(公告)日:2023-11-23
申请号:US18365757
申请日:2023-08-04
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Ping-Hsun LIN , Pei-Cheng HSU , Ching-Fang YU , Ta-Cheng LIEN , Chia-Jen CHEN , Hsin-Chang LEE
IPC: G03F1/24
CPC classification number: G03F1/24
Abstract: An extreme ultraviolet mask including a substrate, a reflective multilayer stack on the substrate and a capping layer on the reflective multilayer stack is provided. The reflective multilayer stack is treated prior to formation of the capping layer on the reflective multilayer stack. The capping layer is formed by an ion-assisted ion beam deposition or an ion-assisted sputtering process.
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公开(公告)号:US20220082928A1
公开(公告)日:2022-03-17
申请号:US17532939
申请日:2021-11-22
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Pei-Cheng HSU , Ta-Cheng LIEN , Hsin-Chang LEE
Abstract: An extreme ultra-violet mask includes a substrate, a multi-layered mirror layer, a capping layer, a first tantalum-containing oxide layer, a tantalum-containing nitride layer, and a second tantalum-containing oxide layer. The multi-layered mirror layer is over the substrate. The capping layer is over the multi-layered mirror layer. The first tantalum-containing oxide layer is over the capping layer. The tantalum-containing nitride layer is over the first tantalum-containing oxide layer. The second tantalum-containing oxide layer is over the tantalum-containing nitride layer.
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公开(公告)号:US20210364906A1
公开(公告)日:2021-11-25
申请号:US17065712
申请日:2020-10-08
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Pei-Cheng HSU , Ta-Cheng LIEN , Hsin-Chang LEE
IPC: G03F1/24 , G03F1/54 , H01L21/027 , H01L21/033
Abstract: In a method of manufacturing a reflective mask, a photo resist layer is formed over a mask blank. The mask blank includes a substrate, a reflective multilayer on the substrate, a capping layer on the reflective multilayer, an absorber layer on the capping layer and a hard mask layer, and the absorber layer is made of Cr, CrO or CrON. The photo resist layer is patterned, the hard mask layer is patterned by using the patterned photo resist layer, the absorber layer is patterned by using the patterned hard mask layer, and an additional element is introduced into the patterned absorber layer to form a converted absorber layer.
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公开(公告)号:US20200004133A1
公开(公告)日:2020-01-02
申请号:US16441700
申请日:2019-06-14
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Pei-Cheng HSU , Chi-Ping WEN , Tzu Yi WANG , Ta-Cheng LIEN , Hsin-Chang LEE
IPC: G03F1/22
Abstract: A method of manufacturing an extreme ultraviolet (EUV) lithography mask includes forming an image pattern in an absorption layer of EUV mask blank. The EUV mask blank includes: a multilayer stack including alternating molybdenum (Mo) and silicon (Si) layers disposed over a first surface of a mask substrate, a capping layer disposed over the multilayer stack, and an absorption layer disposed over the capping layer. A border region surrounds the image pattern having a trench wherein the absorption layer, the capping layer and at least a portion of the multilayer stack are etched. Concave sidewalls are formed in the border region or an inter-diffused portion is formed in the multilayer stack of the trench.
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公开(公告)号:US20150331309A1
公开(公告)日:2015-11-19
申请号:US14278678
申请日:2014-05-15
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Wen-Chang HSUEH , Chia-Jen CHEN , Ta-Cheng LIEN , Hsin-Chang LEE
IPC: G03F1/32
Abstract: A reticle and a method of fabricating the reticle are provided. In various embodiments, the reticle includes a substrate, a patterned first attenuating layer, a patterned second attenuating layer, and a patterned third attenuating layer. The patterned first attenuating layer is disposed on the substrate. The patterned second attenuating layer is disposed on the patterned first attenuating layer. The patterned third attenuating layer is disposed on the patterned second attenuating layer. A first part of the patterned first attenuating layer, a first part of patterned second attenuating layer, and the patterned third attenuating layer are stacked on the substrate as a binary intensity mask portion.
Abstract translation: 提供了掩模版和制作掩模版的方法。 在各种实施例中,掩模版包括衬底,图案化的第一衰减层,图案化的第二衰减层和图案化的第三衰减层。 图案化的第一衰减层设置在基板上。 图案化的第二衰减层设置在图案化的第一衰减层上。 图案化的第三衰减层设置在图案化的第二衰减层上。 图案化第一衰减层的第一部分,图案化第二衰减层的第一部分和图案化的第三衰减层作为二值强度掩模部分堆叠在基板上。
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