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21.发明申请公开(公告)号：US20200161574A1
公开(公告)日：2020-05-21
申请号：US16590115
申请日：2019-10-01
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Timothy Vasen , Marcus Johannes Henricus Van Dal , Gerben Doornbos
Abstract: In a method of forming a gate-all-around field effect transistor, a gate structure is formed surrounding a channel portion of a carbon nanotube. An inner spacer is formed surrounding a source/drain extension portion of the carbon nanotube, which extends outward from the channel portion of the carbon nanotube. The inner spacer includes two dielectric layers that form interface dipole. The interface dipole introduces doping to the source/drain extension portion of the carbon nanotube.
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公开(公告)号：US20240365569A1
公开(公告)日：2024-10-31
申请号：US18769091
申请日：2024-07-10
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Marcus Johannes Henricus Van Dal , Timothy Vasen , Gerben Doornbos
CPC classification number: H10K10/484 , H10K10/491 , H10K19/10 , H10K85/221
Abstract: The current disclosure describes techniques for forming semiconductor structures having multiple semiconductor strips configured as channel portions. In the semiconductor structures, diffusion break structures are formed after the gate structures are formed so that the structural integrity of the semiconductor strips adjacent to the diffusion break structures will not be compromised by a subsequent gate formation process. The diffusion break extends downward from an upper surface until all the semiconductor strips of the adjacent channel portions are truncated by the diffusion break.
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23.发明授权公开(公告)号：US12069874B2
公开(公告)日：2024-08-20
申请号：US18311730
申请日：2023-05-03
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Marcus Johannes Henricus Van Dal , Timothy Vasen , Gerben Doornbos
CPC classification number: H10K10/481 , H10K10/486 , H10K10/84 , H10K19/10 , H10K71/60 , H10K85/221
Abstract: In a method of forming a gate-all-around field effect transistor, a gate structure is formed surrounding a channel portion of a carbon nanotube. An inner spacer is formed surrounding a source/drain extension portion of the carbon nanotube, which extends outward from the channel portion of the carbon nanotube. The inner spacer includes two dielectric layers that form interface dipole. The interface dipole introduces doping to the source/drain extension portion of the carbon nanotube.
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公开(公告)号：US20230301120A1
公开(公告)日：2023-09-21
申请号：US18311839
申请日：2023-05-03
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Marcus Johannes Henricus Van Dal , Timothy Vasen , Gerben Doornbos
CPC classification number: H10K10/484 , H10K10/491 , H10K19/10 , H10K85/221
Abstract: The current disclosure describes techniques for forming semiconductor structures having multiple semiconductor strips configured as channel portions. In the semiconductor structures, diffusion break structures are formed after the gate structures are formed so that the structural integrity of the semiconductor strips adjacent to the diffusion break structures will not be compromised by a subsequent gate formation process. The diffusion break extends downward from an upper surface until all the semiconductor strips of the adjacent channel portions are truncated by the diffusion break.
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公开(公告)号：US11728418B2
公开(公告)日：2023-08-15
申请号：US17735985
申请日：2022-05-03
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Timothy Vasen , Gerben Doornbos , Matthias Passlack
IPC: H01L29/06 , H01L29/775 , H01L29/205 , H01L29/66 , H01L29/10 , H01L29/08
CPC classification number: H01L29/775 , H01L29/0847 , H01L29/1037 , H01L29/205 , H01L29/66462
Abstract: The current disclosure describes a tunnel FET device including a P-I-N heterojunction structure. A high-K dielectric layer and a metal gate wrap around the intrinsic channel layer with an interlayer positioned between high-K dielectric layer and the intrinsic channel layer of the P-I-N heterojunction. The interlayer prevents charge carriers from reaching the interface with high-K dielectric layer under the trap-assisted tunneling effect and reduces OFF state leakage.
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Patent Agency Ranking
26.发明授权公开(公告)号：US11659721B2
公开(公告)日：2023-05-23
申请号：US17374804
申请日：2021-07-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Timothy Vasen , Marcus Johannes Henricus Van Dal , Gerben Doornbos
CPC classification number: H01L51/055 , H01L27/283 , H01L51/0021 , H01L51/0562 , H01L51/105 , H01L51/0048
Abstract: In a method of forming a gate-all-around field effect transistor, a gate structure is formed surrounding a channel portion of a carbon nanotube. An inner spacer is formed surrounding a source/drain extension portion of the carbon nanotube, which extends outward from the channel portion of the carbon nanotube. The inner spacer includes two dielectric layers that form interface dipole. The interface dipole introduces doping to the source/drain extension portion of the carbon nanotube.
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公开(公告)号：US11653507B2
公开(公告)日：2023-05-16
申请号：US17680199
申请日：2022-02-24
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Marcus Johannes Henricus Van Dal , Timothy Vasen , Gerben Doornbos
CPC classification number: H01L51/0558 , H01L27/283 , H01L51/0048 , H01L51/057
Abstract: The current disclosure describes techniques for forming semiconductor structures having multiple semiconductor strips configured as channel portions. In the semiconductor structures, diffusion break structures are formed after the gate structures are formed so that the structural integrity of the semiconductor strips adjacent to the diffusion break structures will not be compromised by a subsequent gate formation process. The diffusion break extends downward from an upper surface until all the semiconductor strips of the adjacent channel portions are truncated by the diffusion break.
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公开(公告)号：US11411103B2
公开(公告)日：2022-08-09
申请号：US15930285
申请日：2020-05-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Timothy Vasen , Gerben Doornbos , Matthias Passlack
IPC: H01L29/06 , H01L29/775 , H01L29/205 , H01L29/66 , H01L29/10 , H01L29/08
Abstract: The current disclosure describes a tunnel FET device including a P-I-N heterojunction structure. A high-K dielectric layer and a metal gate wrap around the intrinsic channel layer with an interlayer positioned between high-K dielectric layer and the intrinsic channel layer of the P-I-N heterojunction. The interlayer prevents charge carriers from reaching the interface with high-K dielectric layer under the trap-assisted tunneling effect and reduces OFF state leakage.
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公开(公告)号：US20210043839A1
公开(公告)日：2021-02-11
申请号：US17068736
申请日：2020-10-12
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
IPC: H01L51/00 , C23C16/455 , C23C16/56 , H01L23/544
Abstract: Provided herein are wafers that can be used to align carbon nanotubes, as well as methods of making and using the same. Such wafers include alignment areas that have four sides and a surface charge, where the alignment areas are surrounded by areas that have a surface charge of a different polarity. Methods of the disclosure may include depositing and selectively etching a number of hardmasks on a substrate. The described methods may also include depositing a carbon nanotube on such a wafer.
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公开(公告)号：US10672899B2
公开(公告)日：2020-06-02
申请号：US16194140
申请日：2018-11-16
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Timothy Vasen , Gerben Doornbos , Matthias Passlack
IPC: H01L29/06 , H01L29/775 , H01L29/205 , H01L29/66 , H01L29/10 , H01L29/08
Abstract: The current disclosure describes a tunnel FET device including a P-I-N heterojunction structure. A high-K dielectric layer and a metal gate wrap around the intrinsic channel layer with an interlayer positioned between high-K dielectric layer and the intrinsic channel layer of the P-I-N heterojunction. The interlayer prevents charge carriers from reaching the interface with high-K dielectric layer under the trap-assisted tunneling effect and reduces OFF state leakage.
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