公开(公告)号：US12237228B2

公开(公告)日：2025-02-25

申请号：US18345148

申请日：2023-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Jyun Wu ,  Hung-Chi Wu ,  Chia-Ching Lee ,  Pin-Hsuan Yeh ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Chien-Hao Chen ,  Sheng-Liang Pan ,  Huan-Just Lin

IPC: H01L21/02 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.

公开(公告)号：US12142530B2

公开(公告)日：2024-11-12

申请号：US17365057

申请日：2021-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Chien-Hao Chen ,  Ching-Hwanq Su

IPC: H01L21/8234 ,  H01L27/088

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.

公开(公告)号：US11916146B2

公开(公告)日：2024-02-27

申请号：US17658708

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Po-Cheng Chen ,  Kuo-Chan Huang ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Chien-Hao Chen

IPC: H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7851 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/42372 ,  H01L29/4966 ,  H01L29/66545

Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

公开(公告)号：US20230386926A1

公开(公告)日：2023-11-30

申请号：US18363945

申请日：2023-08-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Lee ,  Hsin-Han Tsai ,  Shih-Hang Chiu ,  Tsung-Ta Tang ,  Chung-Chiang Wu ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Da-Yuan Lee ,  Jian-Hao Chen ,  Chien-Hao Chen ,  Kuo-Feng Yu ,  Chia-Wei Chen ,  Chih-Yu Hsu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/40 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L21/82345 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/66545 ,  H01L29/4966

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

公开(公告)号：US20220328683A1

公开(公告)日：2022-10-13

申请号：US17852755

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Neng Lin ,  Ming-Hsi Yeh ,  Hung-Chin Chung ,  Hsin-Yun Hsu

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092

Abstract: A semiconductor device includes a first fin, a second fin, and a third fin protruding above a substrate, where the third fin is between the first fin and the second fin; a gate dielectric layer over the first fin, the second fin, and the third fin; a first work function layer over and contacting the gate dielectric layer, where the first work function layer extends along first sidewalls and a first upper surface of the first fin; a second work function layer over and contacting the gate dielectric layer, where the second work function layer extends along second sidewalls and a second upper surface of the second fin, where the first work function layer and the second work function layer comprise different materials; and a first gate electrode over the first fin, a second gate electrode over the second fin, and a third gate electrode over the third fin.

公开(公告)号：US11437280B2

公开(公告)日：2022-09-06

申请号：US16900439

申请日：2020-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Lee ,  Hsin-Han Tsai ,  Shih-Hang Chiu ,  Tsung-Ta Tang ,  Chung-Chiang Wu ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Da-Yuan Lee ,  Jian-Hao Chen ,  Chien-Hao Chen ,  Kuo-Feng Yu ,  Chia-Wei Chen ,  Chih-Yu Hsu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/40 ,  H01L29/66

Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.

公开(公告)号：US11302818B2

公开(公告)日：2022-04-12

申请号：US16571879

申请日：2019-09-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chiang Wu ,  Po-Cheng Chen ,  Kuo-Chan Huang ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Chien-Hao Chen

IPC: H01L29/423 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/40 ,  H01L29/49

Abstract: A device includes a semiconductor fin, and a gate stack on sidewalls and a top surface of the semiconductor fin. The gate stack includes a high-k dielectric layer, a work-function layer overlapping a bottom portion of the high-k dielectric layer, and a blocking layer overlapping a second bottom portion of the work-function layer. A low-resistance metal layer overlaps and contacts the work-function layer and the blocking layer. The low-resistance metal layer has a resistivity value lower than second resistivity values of both of the work-function layer and the blocking layer. A gate spacer contacts a sidewall of the gate stack.

公开(公告)号：US20210082768A1

公开(公告)日：2021-03-18

申请号：US16568518

申请日：2019-09-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Jyun Wu ,  Hung-Chi Wu ,  Chia-Ching Lee ,  Pin-Hsuan Yeh ,  Hung-Chin Chung ,  Hsien-Ming Lee ,  Chien-Hao Chen ,  Sheng-Liang Pan ,  Huan-Just Lin

IPC: H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: An improved work function layer and a method of forming the same are disclosed. In an embodiment, the method includes forming a semiconductor fin extending from a substrate; depositing a dielectric layer over the semiconductor fin; depositing a first work function layer over the dielectric layer; and exposing the first work function layer to a metastable plasma of a first reaction gas, a metastable plasma of a generation gas, and a metastable plasma of a second reaction gas, the first reaction gas being different from the second reaction gas.

公开(公告)号：US20200083108A1

公开(公告)日：2020-03-12

申请号：US16686388

申请日：2019-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yen Tsai ,  Chung-Chiang Wu ,  Tai-Wei Hwang ,  Hung-Chin Chung ,  Wei-Chin Lee ,  Da-Yuan Lee ,  Ching-Hwanq Su ,  Yin-Chuan Chuang ,  Kuan-Ting Liu

IPC: H01L21/8234 ,  H01L29/51 ,  H01L21/02 ,  H01L27/088

Abstract: Embodiments disclosed herein relate to a pre-deposition treatment of materials utilized in metal gates of different transistors on a semiconductor substrate. In an embodiment, a method includes exposing a first metal-containing layer of a first device and a second metal-containing layer of a second device to a reactant to form respective monolayers on the first and second metal-containing layers. The first and second devices are on a substrate. The first device includes a first gate structure including the first metal-containing layer. The second device includes a second gate structure including the second metal-containing layer different from the second metal-containing layer. The monolayers on the first and second metal-containing layers are exposed to an oxidant to provide a hydroxyl group (—OH) terminated surface for the monolayers. Thereafter, a third metal-containing layer is formed on the —OH terminated surfaces of the monolayers on the first and second metal-containing layers.

公开(公告)号：US20240387679A1

公开(公告)日：2024-11-21

申请号：US18787716

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ching Lee ,  Hung-Chin Chung ,  Chung-Chiang Wu ,  Hsuan-Yu Tung ,  Kuan-Chang Chiu ,  Chien-Hao Chen ,  Chi On Chui

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device and method of manufacture are provided. In some embodiments a treatment process is utilized to treat a work function layer. The treatment prevents excessive oxidation of the work function layer during subsequent processing steps, such as application of a subsequent photoresist material, thereby allowing the work function layer to be thinner than otherwise.