公开(公告)号：US11552068B2

公开(公告)日：2023-01-10

申请号：US17214703

申请日：2021-03-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Fong-Yuan Chang ,  Kuo-Nan Yang ,  Chung-Hsing Wang ,  Lee-Chung Lu ,  Sheng-Fong Chen ,  Po-Hsiang Huang ,  Hiranmay Biswas ,  Sheng-Hsiung Chen ,  Aftab Alam Khan

IPC: H01L27/02 ,  H01L23/522 ,  H01L27/118 ,  G06F30/394

Abstract: A method includes forming a cell layer including first and second cells, each of which is configured to perform a circuit function; forming a first metal layer above the cell layer and including a first conductive feature and a second conductive feature extending along a first direction, in which the first conductive feature extends from the first cell into the second cell, and in which a shortest distance between a center line of the first conductive feature and a center line of the second conductive feature along a second direction is less than a width of the first conductive feature, and the second direction is perpendicular to the first direction; forming a first conductive via interconnecting the cell layer and the conductive feature.

公开(公告)号：US11366951B2

公开(公告)日：2022-06-21

申请号：US17204275

申请日：2021-03-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Shen Lin ,  Ming-Hsien Lin ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: G06F30/398 ,  G06F30/394 ,  G06F30/367

Abstract: A failure-in-time (FIT) evaluation method for an IC is provided. The FIT evaluation method includes accessing data representing a layout of the IC including a metal line and a plurality of vertical interconnect accesses (VIAs); picking a plurality of nodes along the metal line; dividing the metal line into a plurality of metal segments based on the nodes; and determining FIT value for each of the metal segments to verify the layout and fabricate the IC. The number of the nodes is less than the number of the VIAs, and a distance between two adjacent VIAs of the VIAs is less than a width of the metal line.

公开(公告)号：US10157254B2

公开(公告)日：2018-12-18

申请号：US15361970

申请日：2016-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Nan Yang ,  Chung-Hsing Wang ,  Yi-Kan Cheng ,  Kumar Lalgudi

IPC: G06F17/50 ,  H01L23/528 ,  H03K5/15

Abstract: In some embodiments, the present disclosure relates to a clock tree structure disposed on a semiconductor substrate. The clock tree structure includes a first clock line having a first line width and being arranged at a first height as measured from an upper surface of the semiconductor substrate. The clock tree structure also includes a second clock line having a second line width, which differs from the first line width. The second clock line is arranged at a second height as measured from the upper surface of the semiconductor substrate and the second height is equal to the first height. The first line width can be directly proportional to a first current level for the first clock line and the second line width can be directly proportional to a second current level for the second clock line.

公开(公告)号：US09564896B2

公开(公告)日：2017-02-07

申请号：US14296042

申请日：2014-06-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jerry Chang-Jui Kao ,  Chien-Ju Chao ,  Chin-Shen Lin ,  Nitesh Katta ,  Kuo-Nan Yang ,  Chung-Hsing Wang

IPC: H03K19/00 ,  H02M3/157 ,  H02M3/155 ,  H02M1/00 ,  H02M3/156

CPC classification number: H03K19/0013 ,  H02M3/155 ,  H02M3/156 ,  H02M3/157 ,  H02M2001/0012

Abstract: A circuit is disclosed that includes a plurality of voltage control circuits and a control module. Each of the voltage control circuits is controlled by a control signal. The control module is configured to generate the control signal and to determine a voltage level or a pulse width of the control signal in accordance with a current process corner condition of the voltage control circuits and at least one of first predetermined data and second predetermined data.

Abstract translation: 公开了包括多个电压控制电路和控制模块的电路。 每个电压控制电路由控制信号控制。 控制模块被配置为产生控制信号并且根据电压控制电路的当前处理转角条件和第一预定数据和第二预定数据中的至少一个来确定控制信号的电压电平或脉冲宽度。