CULTURING SYSTEM
    21.
    发明申请
    CULTURING SYSTEM 审中-公开
    文化系统

    公开(公告)号:US20100009433A1

    公开(公告)日:2010-01-14

    申请号:US12496059

    申请日:2009-07-01

    申请人: Hiroyuki Kimura

    发明人: Hiroyuki Kimura

    IPC分类号: C12M1/00

    CPC分类号: C12M41/36 C12M29/06 C12M41/14

    摘要: The problem of a specimen being vibrated during supply or drainage of a liquid such as a culture solution can be avoided, thus allowing acquisition of a stable image. The invention provides a culturing system including a main container having an opening facing upward, accommodating a culture vessel containing a biological specimen, and having an inner space maintained at a predetermined incubation environment; and a nozzle fixed to the main container and inserted into the culture vessel through the opening of the culture vessel to supply or drain a liquid into or from the culture vessel. The main container includes a transparent portion through which the biological specimen in the main container can be externally observed.

    摘要翻译: 可以避免样品在诸如培养液的液体的供给或排出期间振动的问题,从而可以获得稳定的图像。 本发明提供一种培养系统,包括:主容器,其具有面向上的开口,容纳含有生物样本的培养容器,并具有保持在预定孵育环境的内部空间; 以及固定在主容器上的喷嘴,并通过培养容器的开口插入培养容器中,以将液体供入或排出培养容器。 主容器包括透明部分,可以从外部观察主容器中的生物样本。

    Ripple filter circuit
    22.
    发明授权
    Ripple filter circuit 有权
    波纹滤波电路

    公开(公告)号:US07495939B2

    公开(公告)日:2009-02-24

    申请号:US11557388

    申请日:2006-11-07

    申请人: Hiroyuki Kimura

    发明人: Hiroyuki Kimura

    IPC分类号: H02M1/14

    CPC分类号: H02M1/15

    摘要: A ripple filter circuit for ensuring the driving of a driving subject while efficiently eliminating ripple even when the operational voltage margin is small. A first transistor, which is connected to a power supply voltage line, is connected to a ground line via a load of the driving subject. A second transistor, which has substantially the same characteristics as the first transistor, and a dummy load are arranged between the power supply voltage line and the ground line. An operational amplifier includes an inverting input terminal, connected between the second transistor and the dummy load, and a non-inverting terminal at which the voltage is decreased by a predetermined voltage from the power supply voltage. The operational amplifier also includes an output connected to the gate terminal of the second transistor and to the gate terminal of the first transistor via a lowpass filter.

    摘要翻译: 波纹滤波器电路,用于确保驱动对象的驱动,同时即使当操作电压裕度小时也有效地消除纹波。 连接到电源电压线的第一晶体管通过驱动对象的负载连接到接地线。 具有与第一晶体管基本相同的特性的第二晶体管和虚设负载设置在电源电压线和接地线之间。 运算放大器包括连接在第二晶体管和虚拟负载之间的反相输入端子和电压从电源电压降低预定电压的同相端子。 运算放大器还包括经由低通滤波器连接到第二晶体管的栅极端子和第一晶体管的栅极端子的输出。

    Oscillator circuit with a voltage restriction block
    23.
    发明授权
    Oscillator circuit with a voltage restriction block 有权
    具有电压限制块的振荡器电路

    公开(公告)号:US07443256B2

    公开(公告)日:2008-10-28

    申请号:US11775230

    申请日:2007-07-10

    申请人: Hiroyuki Kimura

    发明人: Hiroyuki Kimura

    IPC分类号: H03K3/282

    CPC分类号: H03K4/50

    摘要: An oscillator circuit having a relatively simple circuit structure while enabling full swing with low power consumption includes an oscillation core block, a voltage restriction block, and a differential output block. Drain terminals of first and second transistors are each connected to the voltage restriction block. The voltage restriction block restricts the amplitude of an oscillation signal to a reference voltage. Source terminals of third and fourth transistors are connected to drain terminals of fifth and sixth transistors, and source terminals of seventh and eighth transistors are connected to drain terminals of ninth and tenth transistors. This supplies the differential output block with current generated by the amplitude restriction. The differential output block converts the current into drive voltage to ground voltage to perform full swing.

    摘要翻译: 具有相对简单的电路结构同时能够实现全功能低功耗的振荡器电路包括振荡磁芯块,电压限制块和差分输出块。 第一和第二晶体管的漏极端子都连接到电压限制块。 电压限制块将振荡信号的幅度限制为参考电压。 第三和第四晶体管的源极端子连接到第五和第六晶体管的漏极端子,第七和第八晶体管的源极端子连接到第九和第十晶体管的漏极端子。 由差分输出块提供由幅度限制产生的电流。 差分输出块将电流转换为驱动电压至地电压,以进行全速摆幅。

    SERIES REGULATOR CIRCUIT
    24.
    发明申请
    SERIES REGULATOR CIRCUIT 有权
    系列调节器电路

    公开(公告)号:US20080258696A1

    公开(公告)日:2008-10-23

    申请号:US11854546

    申请日:2007-09-13

    申请人: Hiroyuki Kimura

    发明人: Hiroyuki Kimura

    IPC分类号: G05F1/00

    CPC分类号: G05F1/56

    摘要: A series regulator circuit for reducing current consumption, enabling switching between different current consumption modes, and suppressing output voltage fluctuations. A constant current source 20, connected to an input voltage line, is connected to a ground voltage line via a resistor element 21 and transistor B1. Gate terminals of transistors M2, M4 are connected between the constant current source 20 and transistor B1. The transistor M2 is connected to the input voltage line via a transistor M1 activated in a high current mode. The source terminals of the transistors M2, M4 function as the series regulator circuit output terminal, which is connected to the ground voltage line via a resistor element 23 and transistor M3, activated in a high current mode, or via resistor elements 24, 25. A connection node between the resistor elements 24, 25 is connected to a base voltage of the transistor B1.

    摘要翻译: 一种降低电流消耗的串联调节电路,可实现不同电流消耗模式之间的切换,并抑制输出电压波动。 连接到输入电压线的恒定电流源20经由电阻元件21和晶体管B1连接到接地电压线。 晶体管M 2,M 4的栅极端子连接在恒流源20和晶体管B1之间。 晶体管M 2通过以高电流模式激活的晶体管M 1连接到输入电压线。 晶体管M 2,M 4的源极端子用作串联调节器电路输出端子,其经由电阻器元件23和晶体管M 3连接到接地电压线,以高电流模式激活,或通过电阻器元件24 ,25。 电阻元件24,25之间的连接节点连接到晶体管B1的基极电压。

    Series regulator circuit
    25.
    发明授权
    Series regulator circuit 有权
    串联调节电路

    公开(公告)号:US07414384B2

    公开(公告)日:2008-08-19

    申请号:US11689504

    申请日:2007-03-21

    申请人: Hiroyuki Kimura

    发明人: Hiroyuki Kimura

    IPC分类号: G05F1/56 G05F3/16

    CPC分类号: G05F1/46 H03K17/223

    摘要: A series regulator circuit that enables detection of a voltage drop and reduces consumed current in a static state. A constant current source, which is connected to a power supply voltage line, is connected to a bipolar transistor. The bipolar transistor includes an emitter terminal and base terminal connected to a ground line via first and second resistors, respectively. The constant current source is connected to the source terminal of a PMOS transistor and the gate terminal of an NMOS transistor. The source terminal of the NMOS transistor is connected via third and fourth resistors to the base terminal of the bipolar transistor.

    摘要翻译: 一种串联调节电路,能够检测电压降并减少静态下的消耗电流。 连接到电源电压线的恒定电流源连接到双极晶体管。 双极晶体管包括分别经由第一和第二电阻器连接到接地线的发射极端子和基极端子。 恒流源连接到PMOS晶体管的源极端子和NMOS晶体管的栅极端子。 NMOS晶体管的源极端子经由第三和第四电阻器连接到双极晶体管的基极端子。

    Scanning laser microscope
    26.
    发明申请
    Scanning laser microscope 有权
    扫描激光显微镜

    公开(公告)号:US20080185533A1

    公开(公告)日:2008-08-07

    申请号:US12011947

    申请日:2008-01-30

    IPC分类号: G01J1/58

    摘要: Provided is a scanning laser microscope including a first laser light source for emitting ultrashort pulsed laser light; a scanning unit for two-dimensionally scanning the ultrashort pulsed laser light on a specimen; a second laser light source for emitting continuous laser light; an irradiation-position adjusting unit for performing two-dimensional adjustment of an irradiation position of the continuous laser light on the specimen; an objective lens for focusing the ultrashort pulsed laser light and the continuous laser light onto the specimen and for collecting fluorescence generated in the specimen; a light-detecting unit for detecting the fluorescence, which is split off from a light path between the objective lens and the scanning unit; and a continuous-laser-light switching unit for permitting radiation of the continuous laser light when the light-detecting unit is not detecting required fluorescence from the specimen on the basis of the ultrashort pulsed laser light.

    摘要翻译: 本发明提供一种扫描激光显微镜,其包括用于发射超短脉冲激光的第一激光光源; 用于在样本上二维扫描超短脉冲激光的扫描单元; 用于发射连续激光的第二激光光源; 照射位置调整单元,其对所述检体上的所述连续激光的照射位置进行二维调整; 用于将超短脉冲激光和连续激光聚焦到样本上并用于收集在样本中产生的荧光的物镜; 用于检测从物镜和扫描单元之间的光路分离的荧光的光检测单元; 以及连续激光切换单元,用于当光检测单元基于超短脉冲激光不检测来自样本的所需荧光时,允许连续激光的照射。

    JNK inhibitor
    27.
    发明授权
    JNK inhibitor 失效
    JNK抑制剂

    公开(公告)号:US07402595B2

    公开(公告)日:2008-07-22

    申请号:US10504132

    申请日:2003-02-12

    IPC分类号: C07D217/02 A61K31/47

    摘要: A JNK inhibitor containing a compound having an isoquinolinone skeleton or a salt thereof, such as a compound represented by the formula wherein ring A and ring B are each an optionally substituted benzene ring, X is —O—, —N═, —NR3— or —CHR3—, R2 is an acyl group, an optionally esterified or thioesterified carboxyl group, an optionally substituted carbamoyl group or an optionally substituted amino group and the like, a broken line shows a single bond or a double bond, and R1 is a hydrogen atom, an optionally substituted hydrocarbon group, an optionally substituted heterocyclic group and the like, and the like.

    摘要翻译: 含有异喹啉骨架或其盐的化合物的JNK抑制剂,例如下式表示的化合物,其中环A和环B各自为任选取代的苯环,X为-O-,-N-,-NR- SO 3 - 或-CHR 3 - ,R 2是酰基,任选酯化或硫酯化羧基,任选取代的氨基甲酰基或 任选取代的氨基等,虚线表示单键或双键,R 1是氢原子,任选取代的烃基,任选取代的杂环基等, 等等。

    Five-membered heterocyclic compounds
    28.
    发明授权
    Five-membered heterocyclic compounds 失效
    五元杂环化合物

    公开(公告)号:US07368578B2

    公开(公告)日:2008-05-06

    申请号:US10527426

    申请日:2003-09-09

    摘要: The present invention provides a compound represented by the formula: wherein R1 is an optionally substituted 5-membered heterocyclic group; X, Y and V are the same or different and each is a bond, an oxygen atom, a sulfur atom and the like; Q is a divalent hydrocarbon group having 1 to 20 carbon atoms; ring A is an aromatic ring optionally further having 1 to 3 substituents; Z is —(CH2)n-Z1- or -Z1-(CH2)n— (n is an integer of 0 to 8, Z1 is a bond, an oxygen atom, a sulfur atom and the like); ring B is a nitrogen-containing heterocycle optionally further having 1 to 3 substituents; W is a bond or a divalent hydrocarbon group having 1 to 20 carbon atoms; R2 is a hydrogen atom, a cyano group, —PO(OR9)(OR10) (R9 and R10 are the same or different and each is a hydrogen atom or an optionally substituted hydrocarbon group, and R9 and R10 are optionally bonded to form an optionally substituted ring) and the like, or a salt thereof, which has a superior adipose tissue weight decreasing action, a hypoglycemic action and a hypolipidemic action, and which is useful as an agent for the prophylaxis or treatment of obesity, diabetes mellitus, hyperlipidemia, impaired glucose tolerance, hypertension and the like.

    摘要翻译: 本发明提供由下式表示的化合物:其中R 1是任选取代的5元杂环基; X,Y和V相同或不同,各自为键,氧原子,硫原子等; Q为碳原子数为1〜20的二价烃基; 环A是任选进一步具有1至3个取代基的芳环; Z是 - (CH 2)n - - - - - - - - 1 - (CH 2) (n为0〜8的整数,Z 1为键,氧原子,硫原子等); n为0〜8的整数。 环B是任选进一步具有1至3个取代基的含氮杂环; W是碳原子数为1〜20的键或二价烃基; R 2是氢原子,氰基,-PO(OR 9)(OR 10)(R 10) SUP>和R 10相同或不同,各自为氢原子或任选取代的烃基,R 9和R 10为 任选地键合以形成任选取代的环)等,或其盐,其具有优异的脂肪组织重量减少作用,降血糖作用和降血脂作用,并且其可用作预防或治疗 肥胖症,糖尿病,高脂血症,葡萄糖耐量降低,高血压等。

    OSCILLATOR CIRCUIT
    29.
    发明申请
    OSCILLATOR CIRCUIT 有权
    振荡器电路

    公开(公告)号:US20080007350A1

    公开(公告)日:2008-01-10

    申请号:US11775230

    申请日:2007-07-10

    申请人: Hiroyuki Kimura

    发明人: Hiroyuki Kimura

    IPC分类号: H03L7/00

    CPC分类号: H03K4/50

    摘要: An oscillator circuit having a relatively simple circuit structure while enabling full swing with low power consumption includes an oscillation core block, a voltage restriction block, and a differential output block. Drain terminals of first and second transistors are each connected to the voltage restriction block. The voltage restriction block restricts the amplitude of an oscillation signal to a reference voltage. Source terminals of third and fourth transistors are connected to drain terminals of fifth and sixth transistors, and source terminals of seventh and eighth transistors are connected to drain terminals of ninth and tenth transistors. This supplies the differential output block with current generated by the amplitude restriction. The differential output block converts the current into drive voltage to ground voltage to perform full swing.

    摘要翻译: 具有相对简单的电路结构同时能够实现全功能低功耗的振荡器电路包括振荡磁芯块,电压限制块和差分输出块。 第一和第二晶体管的漏极端子都连接到电压限制块。 电压限制块将振荡信号的幅度限制为参考电压。 第三和第四晶体管的源极端子连接到第五和第六晶体管的漏极端子,第七和第八晶体管的源极端子连接到第九和第十晶体管的漏极端子。 由差分输出块提供由幅度限制产生的电流。 差分输出块将电流转换为驱动电压至地电压,以进行全速摆幅。

    LEVEL SHIFTER CIRCUIT
    30.
    发明申请
    LEVEL SHIFTER CIRCUIT 有权
    水平更换电路

    公开(公告)号:US20070176668A1

    公开(公告)日:2007-08-02

    申请号:US11670398

    申请日:2007-02-01

    申请人: Hiroyuki Kimura

    发明人: Hiroyuki Kimura

    IPC分类号: H03L5/00

    CPC分类号: H03K19/018521

    摘要: A level shifter circuit, which includes a Schmitt trigger function, shifts voltage of a high level signal into a low voltage and shifts a signal at an intermediate value of an input voltage. The level shifter circuit includes an input terminal connected to low and high voltage circuits. The low voltage circuit outputs a low drive voltage or ground voltage. The high voltage circuit outputs a high drive voltage or a high reference voltage, which is supplied to an RS latch circuit via a potential adjustment circuit at a level equal to an output potential at the low voltage circuit. The RS latch circuit uses the output of the potential adjustment circuit when the input voltage shifts to a high level and uses the output of the low voltage circuit when the input voltage shifts to a low level.

    摘要翻译: 包括施密特触发功能的电平移位器电路将高电平信号的电压转换成低电压,并以输入电压的中间值移位信号。 电平移位器电路包括连接到低压和高压电路的输入端子。 低压电路输出低驱动电压或接地电压。 高电压电路输出高的驱动电压或高的参考电压,其通过电位调节电路以等于低电压电路的输出电位的电平提供给RS锁存电路。 当输入电压变为高电平时,RS锁存电路使用电位调整电路的输出,当输入电压变为低电平时,使用低电压电路的输出。