公开(公告)号：US08716835B2

公开(公告)日：2014-05-06

申请号：US13124873

申请日：2009-10-16

申请人： Yuji Ando ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Kazuki Ota

发明人： Yuji Ando ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Kazuki Ota

IPC分类号： H01L29/66 ,  H01L29/737 ,  H01L29/20

CPC分类号： H01L29/7371 ,  H01L29/0649 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/475 ,  H01L29/66318

摘要： A bipolar transistor is provided with an emitter layer, a base layer and a collector layer. The emitter layer is formed above a substrate and is an n-type conductive layer including a first nitride semiconductor. The base layer is formed on the emitter layer and is a p-type conductive including a second nitride semiconductor. The collector layer is formed on the base layer and includes a third nitride semiconductor. The collector layer, the base layer and the emitter layer are formed such that a crystal growth direction to the substrate surface is parallel to a substrate direction of [000-1]. The third nitride semiconductor contains InycAlxcGa1-xc-ycN (0•xc•1, 0•yc•1, 0

摘要翻译： 双极晶体管设置有发射极层，基极层和集电极层。 发射极层形成在衬底之上，并且是包括第一氮化物半导体的n型导电层。 基极层形成在发射极层上，是包含第二氮化物半导体的p型导体。 集电极层形成在基极层上并且包括第三氮化物半导体。 形成集电体层，基极层和发射极层，使得到基板表面的晶体生长方向平行于[000-1]的基板方向。 第三氮化物半导体含有InycAlxcGa1-xc-ycN（0·xc·1,0,0·yc·1,0,0cc·yc·1）。 第三氮化物半导体中的表面侧的a轴长度比基板侧的a轴长短。

公开(公告)号：US08674407B2

公开(公告)日：2014-03-18

申请号：US12919640

申请日：2009-03-12

申请人： Yuji Ando ,  Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Tatsuo Nakayama ,  Hironobu Miyamoto

发明人： Yuji Ando ,  Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Tatsuo Nakayama ,  Hironobu Miyamoto

IPC分类号： H01L29/66

CPC分类号： H01L29/7783 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/7785

摘要： The present invention provides a semiconductor device having such a structure formed by sequentially laminating a lower barrier layer composed of lattice-relaxed AlxGa1-xN (0≦x≦1), a channel layer composed of InyGa1-yN (0≦y≦1) with compressive strain and a contact layer composed of AlzGa1-zN (0≦z≦1), wherein a two-dimensional electron gas is produced in the vicinity of an interface of said InyGa1-yN channel layer with said AlzGa1-zN contact layer; a gate electrode is formed so as to be embedded in the recessed portion with intervention of an insulating film, which recessed portion is formed by removing a part of said AlzGa1-zN contact layer by etching it away until said InyGa1-yN channel layer is exposed; and, ohmic electrodes are formed on the AlzGa1-zN contact layer. Thus, the semiconductor device has superior uniformity and reproducibility of the threshold voltage while maintaining a low gate leakage current, and is also applicable to the enhancement mode type.

摘要翻译： 本发明提供一种具有这样的结构的半导体器件，该半导体器件通过依次层叠由晶格弛豫的Al x Ga 1-x N（0 @ x @ 1）构成的下阻挡层，由InyGa1-yN（0 @ y @ 1） 具有压应变和由Al z Ga 1-z N（0 @ z @ 1）组成的接触层，其中在所述In y Ga 1-y N沟道层与所述Al z Ga 1-z N接触层的界面附近产生二维电子气; 通过介入绝缘膜形成嵌入在凹陷部分中的栅电极，该凹陷部分通过蚀刻除去所述AlzGa1-zN接触层的一部分而形成，直到所述In y Ga 1-y N沟道层暴露 ; 并且在AlzGa1-zN接触层上形成欧姆电极。 因此，半导体器件在保持低栅极漏电流的同时具有优异的阈值电压的均匀性和再现性，并且也适用于增强型。

公开(公告)号：US08525229B2

公开(公告)日：2013-09-03

申请号：US12299542

申请日：2007-05-07

申请人： Yasuhiro Okamoto ,  Yuji Ando ,  Takashi Inoue ,  Tatsuo Nakayama ,  Hironobu Miyamoto

发明人： Yasuhiro Okamoto ,  Yuji Ando ,  Takashi Inoue ,  Tatsuo Nakayama ,  Hironobu Miyamoto

IPC分类号： H01L29/205 ,  H01L29/778

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/42316

摘要： A semiconductor device includes a channel layer, an electron-supplying layer provided on the channel layer, a cap layer provided on the electron-supplying layer and creating lattice match with the channel layer, and ohmic electrodes provided on the cap layer. The cap layer has a composition of (InyAl1-y)zGa1-zN (0≦y≦1, 0≦z≦1). The z for such cap layer monotonically decreases as being farther away from the electron-supplying layer.

摘要翻译： 半导体器件包括沟道层，设置在沟道层上的电子供给层，设置在电子供给层上并与沟道层形成晶格匹配的盖层以及设置在盖层上的欧姆电极。 盖层具有（In y Al 1-y）z Ga 1-z N（0 @ y @ 1，0 @ z @ 1）的组成。 这种盖层的z随着远离电子供应层而单调减小。

公开(公告)号：US20110241075A1

公开(公告)日：2011-10-06

申请号：US13124872

申请日：2009-10-16

申请人： Yuji Ando ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Kazuki Ota

发明人： Yuji Ando ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Kazuki Ota

IPC分类号： H01L29/737

CPC分类号： H01L29/7371 ,  H01L29/045 ,  H01L29/2003

摘要： A bipolar transistor includes: a substrate; a collector and a base layer with a p-conductive-type, an emitter layer with an n-conductive-type. The collector layer is formed above the substrate and includes a first nitride semiconductor. The base layer with the p-conductive-type is formed on the collector layer and includes a second nit ride semiconductor. The emitter layer with the n-conductive-type is formed on the base layer and includes a third nitride semiconductor. The collector layer, the base layer and the emitter layer are formed so that crystal growing directions with respect to a surface of the substrate are in parallel to a [0001] direction of the substrate. The first nitride semiconductor includes: InycAlxcGa1-xc-ycN (0≦xc≦1, 0≦yc≦1, 0

摘要翻译： 双极晶体管包括：基板; 具有p导电型的集电极和基极层，具有n导电型的发射极层。 集电极层形成在衬底上方并且包括第一氮化物半导体。 具有p型导电型的基底层形成在集电极层上，并且包括第二耐磨半导体。 具有n导电型的发射极层形成在基极层上并且包括第三氮化物半导体。 形成集电体层，基极层和发射极层，使得相对于基板的表面的晶体生长方向与基板的[0001]方向平行。 第一氮化物半导体包括：InycAlxcGa1-xc-ycN（0＆nlE; xc＆nlE; 1,0＆amp; nlE; yc＆nlE; 1,0

公开(公告)号：US20060102929A1

公开(公告)日：2006-05-18

申请号：US10538739

申请日：2003-12-15

申请人： Yasuhiro Okamoto ,  Hironobu Miyamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Massaki Kuzuhara

发明人： Yasuhiro Okamoto ,  Hironobu Miyamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Massaki Kuzuhara

IPC分类号： H01L31/109

CPC分类号： H01L29/402 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/7787

摘要： A field plate portion (5) overhanging a drain side in a visored shape is formed in a gate electrode (2). A multilayered film including a SiN film (21) and a SiO2 film (22) is formed beneath the field plate portion (5). The SiN film (21) is formed so that a surface of an AlGaN electron supply layer (13) is covered therewith.

摘要翻译： 在栅电极（2）中形成有以遮挡形状突出于漏极侧的场板部（5）。 在场板部分（5）的下方形成包括SiN膜（21）和SiO 2膜（22）的多层膜。 形成SiN膜（21），使得AlGaN电子供给层（13）的表面被覆盖。

公开(公告)号：US08659055B2

公开(公告)日：2014-02-25

申请号：US13497557

申请日：2010-06-16

申请人： Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yuji Ando

发明人： Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yuji Ando

IPC分类号： H01L29/66 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/1054 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/267 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66734

摘要： Provided is a semiconductor device capable of suppressing an occurrence of a punch-through phenomenon.A semiconductor device includes a substrate 1, a first n-type semiconductor layer 2, a p-type semiconductor layer 3, a second n-type semiconductor layer 4, a drain electrode 13, a source electrode 11, a gate electrode 12, and a gate insulation film 21, wherein the first n-type semiconductor layer 2, the p-type semiconductor layer 3, and the second n-type semiconductor layer 4 are laminated on the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 2. The source electrode 11 is in ohmic-contact with the second n-type semiconductor layer 4. An opening portion to be filled or a notched portion that extends from an upper surface of the second n-type semiconductor layer 4 to an upper part of the first n-type semiconductor layer 2 is formed at a part of the p-type semiconductor layer 3 and a part of the second n-type semiconductor layer 4. The gate electrode 12 is in contact with an upper surface of the first n-type semiconductor layer 2, side surfaces of the p-type semiconductor layer 3, and side surfaces of the second n-type semiconductor layer 4 at inner surfaces of the opening portion to be filled or a surface of the notched portion via the gate insulation film 21. The p-type semiconductor layer 3 has a positive polarization charge at a first n-type semiconductor layer 2 side in a state where a voltage is applied to none of the electrodes.

摘要翻译： 提供能够抑制穿通现象发生的半导体装置。 半导体器件包括衬底1，第一n型半导体层2，p型半导体层3，第二n型半导体层4，漏极13，源电极11，栅电极12和 栅极绝缘膜21，其中第一n型半导体层2，p型半导体层3和第二n型半导体层4依次层压在基板1上。 漏电极13与第一n型半导体层2欧姆接触。源电极11与第二n型半导体层4欧姆接触。要填充的开口部分或延伸的缺口部分 从第二n型半导体层4的上表面到第一n型半导体层2的上部形成在p型半导体层3的一部分上，第二n型半导体层的一部分 栅电极12与第一n型半导体层2的上表面，p型半导体层3的侧表面和第二n型半导体层4的内表面的侧表面接触 待填充的开口部分或经由栅极绝缘膜21的切口部分的表面。在施加电压的状态下，p型半导体层3在第一n型半导体层2侧具有正极化电荷 没有电极。

公开(公告)号：US08552471B2

公开(公告)日：2013-10-08

申请号：US13139789

申请日：2009-12-11

申请人： Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Kazuomi Endo

发明人： Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Kazuomi Endo

IPC分类号： H01L29/66

CPC分类号： H01L29/402 ,  H01L29/0619 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7787

摘要： There is provided a semiconductor apparatus capable of achieving both a reverse blocking characteristic and a low on-resistance. The semiconductor apparatus includes a first semiconductor layer including a channel layer, a source electrode formed on the first semiconductor layer, a drain electrode formed at a distance from the source electrode on the first semiconductor layer, and a gate electrode formed between the source electrode and the drain electrode on the first semiconductor layer. The drain electrode includes a first drain region where reverse current between the first semiconductor layer and the first drain region is blocked, and a second drain region formed at a greater distance from the gate electrode than the first drain region, where a resistance between the first semiconductor layer and the second drain region is lower than a resistance between the first semiconductor layer and the first drain region.

摘要翻译： 提供了能够实现反向阻挡特性和低导通电阻的半导体装置。 半导体装置包括：第一半导体层，包括沟道层，形成在第一半导体层上的源电极，在第一半导体层上与源极间隔一定距离处形成的漏电极，以及形成在源电极和 第一半导体层上的漏电极。 漏电极包括第一漏极区，其中第一半导体层和第一漏极区之间的反向电流被阻挡，以及形成在比栅极电极比第一漏极区更远的距离处的第二漏区， 半导体层和第二漏极区域比第一半导体层和第一漏极区域之间的电阻低。

公开(公告)号：US08395237B2

公开(公告)日：2013-03-12

申请号：US13124872

申请日：2009-10-16

申请人： Yuji Ando ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Kazuki Ota

发明人： Yuji Ando ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Kazuki Ota

IPC分类号： H01L29/66 ,  H01L29/737

CPC分类号： H01L29/7371 ,  H01L29/045 ,  H01L29/2003

摘要： A bipolar transistor includes: a substrate; a collector and a base layer with a p-conductive-type, an emitter layer with an n-conductive-type. The collector layer is formed above the substrate and includes a first nitride semiconductor. The base layer with the p-conductive-type is formed on the collector layer and includes a second nit ride semiconductor. The emitter layer with the n-conductive-type is formed on the base layer and includes a third nitride semiconductor. The collector layer, the base layer and the emitter layer are formed so that crystal growing directions with respect to a surface of the substrate are in parallel to a [0001] direction of the substrate. The first nitride semiconductor includes: InycAlxcGa1-xc-ycN (0≦xc≦1, 0≦yc≦1, 0

摘要翻译： 双极晶体管包括：基板; 具有p导电型的集电极和基极层，具有n导电型的发射极层。 集电极层形成在衬底上方并且包括第一氮化物半导体。 具有p型导电型的基底层形成在集电极层上，并且包括第二耐磨半导体。 具有n导电型的发射极层形成在基极层上并且包括第三氮化物半导体。 形成集电体层，基极层和发射极层，使得相对于基板的表面的晶体生长方向与基板的[0001]方向平行。 第一氮化物半导体包括：InycAlxcGa1-xc-ycN（0＆nlE; xc＆nlE; 1,0＆amp; nlE; yc＆nlE; 1,0

公开(公告)号：US20110260217A1

公开(公告)日：2011-10-27

申请号：US13139789

申请日：2009-12-11

申请人： Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Kazuomi Endo

发明人： Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Kazuomi Endo

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/402 ,  H01L29/0619 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7787

摘要： There is provided a semiconductor apparatus capable of achieving both a reverse blocking characteristic and a low on-resistance. The semiconductor apparatus includes a first semiconductor layer including a channel layer, a source electrode formed on the first semiconductor layer, a drain electrode formed at a distance from the source electrode on the first semiconductor layer, and a gate electrode formed between the source electrode and the drain electrode on the first semiconductor layer. The drain electrode includes a first drain region where reverse current between the first semiconductor layer and the first drain region is blocked, and a second drain region formed at a greater distance from the gate electrode than the first drain region, where a resistance between the first semiconductor layer and the second drain region is lower than a resistance between the first semiconductor layer and the first drain region.

摘要翻译： 提供了能够实现反向阻挡特性和低导通电阻的半导体装置。 半导体装置包括：第一半导体层，包括沟道层，形成在第一半导体层上的源电极，在第一半导体层上与源极间隔一定距离处形成的漏电极，以及形成在源电极和 第一半导体层上的漏电极。 漏电极包括第一漏极区，其中第一半导体层和第一漏极区之间的反向电流被阻挡，以及形成在比栅极电极比第一漏极区更远的距离处的第二漏区， 半导体层和第二漏极区域比第一半导体层和第一漏极区域之间的电阻低。

公开(公告)号：US07863648B2

公开(公告)日：2011-01-04

申请号：US11921854

申请日：2006-06-12

申请人： Hironobu Miyamoto ,  Yuji Ando ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Akio Wakejima ,  Kensuke Kasahara ,  Yasuhiro Murase ,  Kohji Matsunaga ,  Katsumi Yamanoguchi ,  Hidenori Shimawaki

发明人： Hironobu Miyamoto ,  Yuji Ando ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Akio Wakejima ,  Kensuke Kasahara ,  Yasuhiro Murase ,  Kohji Matsunaga ,  Katsumi Yamanoguchi ,  Hidenori Shimawaki

IPC分类号： H01L29/812 ,  H01L21/338

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/404 ,  H01L29/802 ,  H01L29/812

摘要： A field effect transistor (100) exhibiting good performance at high voltage operation and high frequency includes a first field plate electrode (116) and a second field plate electrode (118). The second field plate electrode includes a shielding part (119) located in the region between the first field plate electrode and a drain electrode (114), and serves to shield the first field plate electrode from the drain electrode. When in the cross sectional view in the gate length direction, the length in the gate length direction of an overlap region where the second field plate electrode (118) overlap the upper part of a structure including the first field plate electrode and a gate electrode (113) is designated as Lol, and the gate length is Lg, the relation expressed as 0 ≦Lol/Lg≦1 holds.

摘要翻译： 在高电压运行和高频下表现出良好性能的场效应晶体管（100）包括第一场极板电极（116）和第二场板电极（118）。 第二场板电极包括位于第一场极板电极和漏电极（114）之间的区域中的屏蔽部分（119），用于屏蔽第一场极板电极与漏极电极。 当在栅极长度方向的横截面视图中，第二场板电极（118）与包括第一场极板电极和栅电极的结构的上部重叠的重叠区域的栅极长度方向上的长度（ 113表示为Lol，栅极长度为Lg，表示为0＆nlE; Lol / Lg＆nlE; 1的关系成立。