公开(公告)号：US08772785B2

公开(公告)日：2014-07-08

申请号：US13141448

申请日：2009-11-26

申请人： Yasuhiro Okamoto ,  Hironobu Miyamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Kazuomi Endo

发明人： Yasuhiro Okamoto ,  Hironobu Miyamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Kazuomi Endo

IPC分类号： H01L29/15

CPC分类号： H01L29/872 ,  H01L29/08 ,  H01L29/2003 ,  H01L29/475

摘要： A semiconductor device includes semiconductor layers, an anode electrode, and a cathode electrode. The semiconductor layers include a composition change layer, the anode electrode is electrically connected to one of principal surfaces of the composition change layer through a formation of a Schottky junction between the anode electrode and a part of the semiconductor layers, the cathode electrode is electrically connected to the other of the principal surfaces of the composition change layer through a formation of a junction between the cathode electrode and another part of the semiconductor layers, the anode electrode and the cathode electrode are capable of applying a voltage to the composition change layer in a direction perpendicular to the principal surface.

摘要翻译： 半导体器件包括半导体层，阳极电极和阴极电极。 半导体层包括组成变化层，阳极电极通过在阳极电极和一部分半导体层之间形成肖特基结而与组合物变化层的主表面电连接，阴极电连接 通过在阴极电极和另一部分半导体层之间形成接合而形成组合物变化层的另一个主表面，阳极电极和阴极电极能够向组合物变化层施加电压 方向垂直于主表面。

公开(公告)号：US20110297954A1

公开(公告)日：2011-12-08

申请号：US13141448

申请日：2009-11-26

申请人： Yasuhiro Okamoto ,  Hironobu Miyamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Kazuomi Endo

发明人： Yasuhiro Okamoto ,  Hironobu Miyamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Kazuomi Endo

IPC分类号： H01L29/20 ,  H01L21/329

CPC分类号： H01L29/872 ,  H01L29/08 ,  H01L29/2003 ,  H01L29/475

摘要： [Problem to be Solved] Provided is a semiconductor device in which the trade-off between the pressure resistance and the on-state resistance is improved and the performance is improved.[Solution] The semiconductor device 1 of the present invention comprises semiconductor layers 20 to 23, an anode electrode 12, and a cathode electrode 13, wherein the semiconductor layers include a composition change layer 23, the anode electrode 12 is electrically connected to one of principal surfaces of the composition change layer through a formation of a Schottky junction between the anode electrode 12 and a part of the semiconductor layers, the cathode electrode 13 is electrically connected to the other of the principal surfaces of the composition change layer through a formation of a junction between the cathode electrode 13 and another part of the semiconductor layers, the anode electrode 12 and the cathode electrode 13 are capable of applying a voltage to the composition change layer 23 in a direction perpendicular to the principal surface, andthe composition change layer 23 has composition that changes from a cathode electrode 13 side toward an anode electrode 12 side in the direction perpendicular to the principal surface of the composition change layer, has a negative polarization charge that is generated due to the composition that changes, and contains a donor impurity.

摘要翻译： [待解决的问题]提供了一种半导体器件，其中改善了耐压性和通态电阻之间的折衷，并提高了性能。 [解决方案]本发明的半导体器件1包括半导体层20至23，阳极电极12和阴极电极13，其中半导体层包括组成变化层23，阳极电极12电连接到 通过在阳极12和半导体层的一部分之间形成肖特基结，组成变化层的主表面通过形成阴极电极13而与组合物改变层的另一个主表面电连接 阴极电极13和半导体层的另一部分之间的接合点，阳极电极12和阴极电极13能够在垂直于主表面的方向上向组合物变化层23施加电压，并且组成变化层 23具有从阴极电极13侧向阳极电极12侧变化的组成 具有垂直于组成变化层的主表面的方向具有由于组成变化而产生并且包含施主杂质的负极化电荷。

公开(公告)号：US08552471B2

公开(公告)日：2013-10-08

申请号：US13139789

申请日：2009-12-11

申请人： Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Kazuomi Endo

发明人： Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Kazuomi Endo

IPC分类号： H01L29/66

CPC分类号： H01L29/402 ,  H01L29/0619 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7787

摘要： There is provided a semiconductor apparatus capable of achieving both a reverse blocking characteristic and a low on-resistance. The semiconductor apparatus includes a first semiconductor layer including a channel layer, a source electrode formed on the first semiconductor layer, a drain electrode formed at a distance from the source electrode on the first semiconductor layer, and a gate electrode formed between the source electrode and the drain electrode on the first semiconductor layer. The drain electrode includes a first drain region where reverse current between the first semiconductor layer and the first drain region is blocked, and a second drain region formed at a greater distance from the gate electrode than the first drain region, where a resistance between the first semiconductor layer and the second drain region is lower than a resistance between the first semiconductor layer and the first drain region.

摘要翻译： 提供了能够实现反向阻挡特性和低导通电阻的半导体装置。 半导体装置包括：第一半导体层，包括沟道层，形成在第一半导体层上的源电极，在第一半导体层上与源极间隔一定距离处形成的漏电极，以及形成在源电极和 第一半导体层上的漏电极。 漏电极包括第一漏极区，其中第一半导体层和第一漏极区之间的反向电流被阻挡，以及形成在比栅极电极比第一漏极区更远的距离处的第二漏区， 半导体层和第二漏极区域比第一半导体层和第一漏极区域之间的电阻低。

公开(公告)号：US20110260217A1

公开(公告)日：2011-10-27

申请号：US13139789

申请日：2009-12-11

申请人： Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Kazuomi Endo

发明人： Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Kazuomi Endo

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/402 ,  H01L29/0619 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7787

摘要： There is provided a semiconductor apparatus capable of achieving both a reverse blocking characteristic and a low on-resistance. The semiconductor apparatus includes a first semiconductor layer including a channel layer, a source electrode formed on the first semiconductor layer, a drain electrode formed at a distance from the source electrode on the first semiconductor layer, and a gate electrode formed between the source electrode and the drain electrode on the first semiconductor layer. The drain electrode includes a first drain region where reverse current between the first semiconductor layer and the first drain region is blocked, and a second drain region formed at a greater distance from the gate electrode than the first drain region, where a resistance between the first semiconductor layer and the second drain region is lower than a resistance between the first semiconductor layer and the first drain region.

摘要翻译： 提供了能够实现反向阻挡特性和低导通电阻的半导体装置。 半导体装置包括：第一半导体层，包括沟道层，形成在第一半导体层上的源电极，在第一半导体层上与源极间隔一定距离处形成的漏电极，以及形成在源电极和 第一半导体层上的漏电极。 漏电极包括第一漏极区，其中第一半导体层和第一漏极区之间的反向电流被阻挡，以及形成在比栅极电极比第一漏极区更远的距离处的第二漏区， 半导体层和第二漏极区域比第一半导体层和第一漏极区域之间的电阻低。

公开(公告)号：US08981434B2

公开(公告)日：2015-03-17

申请号：US13393002

申请日：2010-06-23

申请人： Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Kazuomi Endo

发明人： Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Kazuomi Endo

IPC分类号： H01L29/76 ,  H01L29/812 ,  H01L29/201 ,  H01L29/78 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/423

CPC分类号： H01L29/8122 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7809 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/8128

摘要： Provided is a semiconductor device in which the trade-off between the withstand voltage and the on-resistance is improved and the performance is increased. A semiconductor device comprises a substrate 1, a first n-type semiconductor layer 21′, a second n-type semiconductor layer 23, a p-type semiconductor layer 24, and a third n-type semiconductor layer 25′, wherein the first n-type semiconductor layer 21′, the second n-type semiconductor layer 23, the p-type semiconductor layer 24, and the third n-type semiconductor layer 25′ are laminated at the upper side of the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 21′ and the source electrode 12 is in ohmic-contact with the third n-type semiconductor layer 25′. A gate electrode 14 is arranged so as to fill an opening portion to be filled that extends from the third n-type semiconductor layer 25′ to the second n-type semiconductor layer 23, and the gate electrode 14 is in contact with the upper surface of the second n-type semiconductor layer 23, the side surfaces of the p-type semiconductor layer 24, and the side surfaces of the third n-type semiconductor layer 25′. The second n-type semiconductor layer 23 has composition that changes from the drain electrode 13 side toward the source electrode 12 side in the direction perpendicular to the plane of the substrate 1 and contains donor impurity.

摘要翻译： 提供一种半导体器件，其中耐压和导通电阻之间的折衷被提高并且性能提高。 半导体器件包括衬底1，第一n型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'，其中第一n型半导体层 型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'依次层叠在基板1的上侧。 漏电极13与第一n型半导体层21'欧姆接触，源电极12与第三n型半导体层25'欧姆接触。 栅电极14被布置成填充从第三n型半导体层25'延伸到第二n型半导体层23的待填充的开口部分，并且栅电极14与上表面 第二n型半导体层23，p型半导体层24的侧表面和第三n型半导体层25'的侧表面。 第二n型半导体层23具有从垂直于基板1的平面的方向从漏电极13侧向源电极12侧变化的成分，并且含有施主杂质。

公开(公告)号：US20120199889A1

公开(公告)日：2012-08-09

申请号：US13393002

申请日：2010-06-23

申请人： Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Kazuomi Endo

发明人： Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Kazuomi Endo

IPC分类号： H01L29/78

CPC分类号： H01L29/8122 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7809 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/8128

摘要： Provided is a semiconductor device in which the trade-off between the withstand voltage and the on-resistance is improved and the performance is increased.A semiconductor device comprises a substrate 1, a first n-type semiconductor layer 21′, a second n-type semiconductor layer 23, a p-type semiconductor layer 24, and a third n-type semiconductor layer 25′, wherein the first n-type semiconductor layer 21′, the second n-type semiconductor layer 23, the p-type semiconductor layer 24, and the third n-type semiconductor layer 25′ are laminated at the upper side of the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 21′ and the source electrode 12 is in ohmic-contact with the third n-type semiconductor layer 25′. A gate electrode 14 is arranged so as to fill an opening portion to be filled that extends from the third n-type semiconductor layer 25′ to the second n-type semiconductor layer 23, and the gate electrode 14 is in contact with the upper surface of the second n-type semiconductor layer 23, the side surfaces of the p-type semiconductor layer 24, and the side surfaces of the third n-type semiconductor layer 25′. The second n-type semiconductor layer 23 has composition that changes from the drain electrode 13 side toward the source electrode 12 side in the direction perpendicular to the plane of the substrate 1 and contains donor impurity.

摘要翻译： 提供一种半导体器件，其中耐压和导通电阻之间的折衷被提高并且性能提高。 半导体器件包括衬底1，第一n型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'，其中第一n型半导体层 型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'依次层叠在基板1的上侧。 漏电极13与第一n型半导体层21'欧姆接触，源电极12与第三n型半导体层25'欧姆接触。 栅电极14被布置成填充从第三n型半导体层25'延伸到第二n型半导体层23的待填充的开口部分，并且栅电极14与上表面 第二n型半导体层23，p型半导体层24的侧表面和第三n型半导体层25'的侧表面。 第二n型半导体层23具有从垂直于基板1的平面的方向从漏电极13侧向源电极12侧变化的成分，并且含有施主杂质。

公开(公告)号：US20130105811A1

公开(公告)日：2013-05-02

申请号：US13637555

申请日：2010-12-15

申请人： Yuji Ando ,  Takashi Inoue ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Kazuomi Endo

发明人： Yuji Ando ,  Takashi Inoue ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Kazuomi Endo

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/20

CPC分类号： H01L29/78 ,  H01L21/8252 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/66477 ,  H01L29/7785 ,  H01L29/7787

摘要： The present invention provides a field effect transistor which can achieve both of a high threshold voltage and a low on-state resistance, a method for producing the same, and an electronic device. In the field effect transistor, each of a buffer layer 112, a channel layer 113, a barrier layer 114, and a spacer layer 115 is formed of a group-III nitride semiconductor, and each of the upper surfaces thereof is a group-III atomic plane that is perpendicular to a (0001) crystal axis. The lattice-relaxed buffer layer 112, the channel layer 113 having a compressive strain, and the barrier layer 114 having a tensile strain, and the spacer layer 115 having a compressive strain are laminated on a substrate 100 in this order. The gate insulating film 14 is arranged on the spacer layer 115. The gate electrode 15 is arranged on the gate insulating film 14. The source electrode 161 and the drain electrode 162 are electrically connected to the channel layer 113 directly or via another component.

摘要翻译： 本发明提供了能够实现高阈值电压和低通态电阻两者的场效应晶体管，其制造方法和电子器件。 在场效应晶体管中，由III族氮化物半导体形成缓冲层112，沟道层113，势垒层114和间隔层115，其上表面分别为III族 原子平面垂直于（0001）晶轴。 栅格弛豫缓冲层112，具有压缩应变的沟道层113和具有拉伸应变的阻挡层114以及具有压缩应变的间隔层115以此顺序层压在基板100上。 栅极绝缘膜14布置在间隔层115上。栅电极15布置在栅极绝缘膜14上。源极161和漏极162直接或经由另一个部件电连接到沟道层113。

公开(公告)号：US08921894B2

公开(公告)日：2014-12-30

申请号：US13637555

申请日：2010-12-15

申请人： Yuji Ando ,  Takashi Inoue ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Kazuomi Endo

发明人： Yuji Ando ,  Takashi Inoue ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Kazuomi Endo

IPC分类号： H01L29/778 ,  H01L21/8252 ,  H01L29/78 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/78 ,  H01L21/8252 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/66477 ,  H01L29/7785 ,  H01L29/7787

摘要： The present invention provides a field effect transistor which can achieve both of a high threshold voltage and a low on-state resistance, a method for producing the same, and an electronic device. In the field effect transistor, each of a buffer layer 112, a channel layer 113, a barrier layer 114, and a spacer layer 115 is formed of a group-III nitride semiconductor, and each of the upper surfaces thereof is a group-III atomic plane that is perpendicular to a (0001) crystal axis. The lattice-relaxed buffer layer 112, the channel layer 113 having a compressive strain, and the barrier layer 114 having a tensile strain, and the spacer layer 115 having a compressive strain are laminated on a substrate 100 in this order. The gate insulating film 14 is arranged on the spacer layer 115. The gate electrode 15 is arranged on the gate insulating film 14. The source electrode 161 and the drain electrode 162 are electrically connected to the channel layer 113 directly or via another component.

摘要翻译： 本发明提供了能够实现高阈值电压和低通态电阻两者的场效应晶体管，其制造方法和电子器件。 在场效应晶体管中，由III族氮化物半导体形成缓冲层112，沟道层113，势垒层114和间隔层115，其上表面为III族 原子平面垂直于（0001）晶轴。 栅格弛豫缓冲层112，具有压缩应变的沟道层113和具有拉伸应变的阻挡层114以及具有压缩应变的间隔层115以此顺序层压在基板100上。 栅极绝缘膜14布置在间隔层115上。栅电极15布置在栅极绝缘膜14上。源极161和漏极162直接或经由另一个部件电连接到沟道层113。

公开(公告)号：US20130099245A1

公开(公告)日：2013-04-25

申请号：US13637316

申请日：2010-12-15

申请人： Yuji Ando ,  Takashi Inoue ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Kazuomi Endo

发明人： Yuji Ando ,  Takashi Inoue ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Kazuomi Endo

IPC分类号： H01L29/205 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/205 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/66431 ,  H01L29/7785 ,  H01L29/7787 ,  H01L29/78

摘要： The present invention provides a field effect transistor which can achieve both of a high threshold voltage and a low on-state resistance, a method for producing the same, and an electronic device. In the field effect transistor, each of a buffer layer 112, a channel layer 113, a barrier layer 114, and a spacer layer 115 is formed of a group-III nitride semiconductor, and each of the upper surfaces thereof is a group-III atomic plane that is perpendicular to a (0001) crystal axis. The lattice-relaxed buffer layer 112, the lattice-relaxed channel layer 113, and the barrier layer 114 having a tensile strain, and the spacer layer 115 are laminated on a substrate 100 in this order. The gate insulating film 14 is arranged on the spacer layer 115. The gate electrode 15 is arranged on the gate insulating film 14. The source electrode 161 and the drain electrode 162 are electrically connected to the channel layer 113 directly or via another component.

摘要翻译： 本发明提供了能够实现高阈值电压和低通态电阻两者的场效应晶体管，其制造方法和电子器件。 在场效应晶体管中，由III族氮化物半导体形成缓冲层112，沟道层113，势垒层114和间隔层115，其上表面为III族 原子平面垂直于（0001）晶轴。 晶格弛豫缓冲层112，晶格松弛沟道层113和具有拉伸应变的势垒层114和间隔层115依次层压在基板100上。 栅极绝缘膜14布置在间隔层115上。栅电极15布置在栅极绝缘膜14上。源极161和漏极162直接或经由另一个部件电连接到沟道层113。

公开(公告)号：US20110006346A1

公开(公告)日：2011-01-13

申请号：US12919640

申请日：2009-03-12

申请人： Yuji Ando ,  Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Tatsuo Nakayama ,  Hironobu Miyamoto

发明人： Yuji Ando ,  Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Tatsuo Nakayama ,  Hironobu Miyamoto

IPC分类号： H01L29/737

CPC分类号： H01L29/7783 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/518 ,  H01L29/7785

摘要： The present invention provides a semiconductor device that has high electron mobility while reducing a gate leakage current, and superior uniformity and reproducibility of the threshold voltage, and is also applicable to the enhancement mode type. The semiconductor device according to the present invention is a semiconductor device having such a structure formed by sequentially laminating a lower barrier layer composed of lattice-relaxed AlxGa1-xN (0≦x≦1), a channel layer composed of InyGa1-yN (0≦y≦1) with compressive strain and a contact layer composed of AlzGa1-zN (0≦z≦1), wherein a two-dimensional electron gas is produced in the vicinity of an interface of said InyGa1-yN channel layer with said AlzGa1-zN contact layer; a gate electrode is formed so as to be embedded in the recessed portion with intervention of an insulating film, which recessed portion is formed by removing a part of said AlzGa1-zN contact layer by etching it away until said InyGa1-yN channel layer is exposed; and, ohmic electrodes are formed on the AlzGa1-zN contact layer. Thus, there is provided a semiconductor device that has superior uniformity and reproducibility of the threshold voltage while maintaining a low gate leakage current and high electron mobility, and thereby, is capable of operation in enhancement mode.

摘要翻译： 本发明提供了一种在降低栅极漏电流的同时具有高电子迁移率并具有优异的阈值电压的均匀性和再现性的半导体器件，并且也适用于增强型。 根据本发明的半导体器件是具有这样的结构的半导体器件，该半导体器件通过顺序地层叠由晶格弛豫的Al x Ga 1-x N（0＆lt; n 1; x＆n 1; 1）构成的下阻挡层，由InyGa1-yN（0＆ ; y＆nlE; 1）具有压应变和由AlzGa1-zN（0＆amp; nlE; z＆nlE; 1）组成的接触层，其中在所述In y Ga 1-y N沟道层的界面附近产生二维电子气体与所述AlzGa1 -zN接触层 通过介入绝缘膜形成嵌入在凹陷部分中的栅电极，该凹陷部分通过蚀刻除去所述AlzGa1-zN接触层的一部分而形成，直到所述In y Ga 1-y N沟道层暴露 ; 并且在AlzGa1-zN接触层上形成欧姆电极。 因此，提供了具有优异的阈值电压的均匀性和再现性的半导体器件，同时保持低栅极漏电流和高电子迁移率，从而能够在增强模式下操作。