公开(公告)号：US09240858B2

公开(公告)日：2016-01-19

申请号：US13988444

申请日：2011-11-22

申请人： Kazuomi Endo ,  Yoichi Hashimoto

发明人： Kazuomi Endo ,  Yoichi Hashimoto

IPC分类号： H04B10/00 ,  H04J14/06 ,  H04B10/556 ,  H04B10/61

CPC分类号： H04J14/06 ,  H04B10/5561 ,  H04B10/6166

摘要： In order to perform the polarization demultiplexing of the polarization multiplexed BPSK signal using a small-scale circuit by means of optical phase modulation of the polarization multiplexed BPSK signal into the pseudo polarization multiplexed QPSK signal, an optical communication system for communicating by using polarization multiplexed optical signals includes an optical phase modulation means for modulating phases of a plurality of optical signals employing BPSK modulation system including information to be communicated, and for generating a plurality of optical signals to become signals by pseudo QPSK modulation system; and a signal restoration means for performing polarization demultiplexing of a plurality of polarization multiplexed optical signals from a plurality of optical signals modulated into the pseudo QPSK modulation system, and for restoring the information to be communicated.

摘要翻译： 为了通过偏振多路复用的BPSK信号的光相位调制使用小尺度电路将偏振复用的BPSK信号的偏振解复用进入伪偏振复用的QPSK信号，通过使用偏振复用光信号进行通信的光通信系统 信号包括光相位调制装置，用于使用包括要传送的信息的BPSK调制系统来调制多个光信号的相位，并且用于通过伪QPSK调制系统产生多个光信号成为信号; 以及信号恢复装置，用于从被调制到伪QPSK调制系统的多个光信号中进行多个偏振复用光信号的偏振解复用，并用于恢复要传送的信息。

公开(公告)号：US20130243434A1

公开(公告)日：2013-09-19

申请号：US13988444

申请日：2011-11-22

申请人： Kazuomi Endo ,  Yoichi Hashimoto

发明人： Kazuomi Endo ,  Yoichi Hashimoto

IPC分类号： H04J14/06

CPC分类号： H04J14/06 ,  H04B10/5561 ,  H04B10/6166

摘要： In order to perform the polarization demultiplexing of the polarization multiplexed BPSK signal using a small-scale circuit by means of optical phase modulation of the polarization multiplexed BPSK signal into the pseudo polarization multiplexed QPSK signal, an optical communication system for communicating by using polarization multiplexed optical signals includes an optical phase modulation means for modulating phases of a plurality of optical signals employing BPSK modulation system including information to be communicated, and for generating a plurality of optical signals to become signals by pseudo QPSK modulation system; and a signal restoration means for performing polarization demultiplexing of a plurality of polarization multiplexed optical signals from a plurality of optical signals modulated into the pseudo QPSK modulation system, and for restoring the information to be communicated.

摘要翻译： 为了通过偏振多路复用的BPSK信号的光相位调制使用小尺度电路将偏振复用的BPSK信号的偏振解复用进入伪偏振复用的QPSK信号，通过使用偏振复用光信号进行通信的光通信系统 信号包括光相位调制装置，用于使用包括要传送的信息的BPSK调制系统来调制多个光信号的相位，并且用于通过伪QPSK调制系统产生多个光信号成为信号; 以及信号恢复装置，用于从被调制到伪QPSK调制系统的多个光信号中进行多个偏振复用光信号的偏振解复用，并用于恢复要传送的信息。

公开(公告)号：US08981434B2

公开(公告)日：2015-03-17

申请号：US13393002

申请日：2010-06-23

申请人： Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Kazuomi Endo

发明人： Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Kazuomi Endo

IPC分类号： H01L29/76 ,  H01L29/812 ,  H01L29/201 ,  H01L29/78 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/423

CPC分类号： H01L29/8122 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7809 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/8128

摘要： Provided is a semiconductor device in which the trade-off between the withstand voltage and the on-resistance is improved and the performance is increased. A semiconductor device comprises a substrate 1, a first n-type semiconductor layer 21′, a second n-type semiconductor layer 23, a p-type semiconductor layer 24, and a third n-type semiconductor layer 25′, wherein the first n-type semiconductor layer 21′, the second n-type semiconductor layer 23, the p-type semiconductor layer 24, and the third n-type semiconductor layer 25′ are laminated at the upper side of the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 21′ and the source electrode 12 is in ohmic-contact with the third n-type semiconductor layer 25′. A gate electrode 14 is arranged so as to fill an opening portion to be filled that extends from the third n-type semiconductor layer 25′ to the second n-type semiconductor layer 23, and the gate electrode 14 is in contact with the upper surface of the second n-type semiconductor layer 23, the side surfaces of the p-type semiconductor layer 24, and the side surfaces of the third n-type semiconductor layer 25′. The second n-type semiconductor layer 23 has composition that changes from the drain electrode 13 side toward the source electrode 12 side in the direction perpendicular to the plane of the substrate 1 and contains donor impurity.

摘要翻译： 提供一种半导体器件，其中耐压和导通电阻之间的折衷被提高并且性能提高。 半导体器件包括衬底1，第一n型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'，其中第一n型半导体层 型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'依次层叠在基板1的上侧。 漏电极13与第一n型半导体层21'欧姆接触，源电极12与第三n型半导体层25'欧姆接触。 栅电极14被布置成填充从第三n型半导体层25'延伸到第二n型半导体层23的待填充的开口部分，并且栅电极14与上表面 第二n型半导体层23，p型半导体层24的侧表面和第三n型半导体层25'的侧表面。 第二n型半导体层23具有从垂直于基板1的平面的方向从漏电极13侧向源电极12侧变化的成分，并且含有施主杂质。

公开(公告)号：US08921894B2

公开(公告)日：2014-12-30

申请号：US13637555

申请日：2010-12-15

申请人： Yuji Ando ,  Takashi Inoue ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Kazuomi Endo

发明人： Yuji Ando ,  Takashi Inoue ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Kazuomi Endo

IPC分类号： H01L29/778 ,  H01L21/8252 ,  H01L29/78 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/78 ,  H01L21/8252 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/66477 ,  H01L29/7785 ,  H01L29/7787

摘要： The present invention provides a field effect transistor which can achieve both of a high threshold voltage and a low on-state resistance, a method for producing the same, and an electronic device. In the field effect transistor, each of a buffer layer 112, a channel layer 113, a barrier layer 114, and a spacer layer 115 is formed of a group-III nitride semiconductor, and each of the upper surfaces thereof is a group-III atomic plane that is perpendicular to a (0001) crystal axis. The lattice-relaxed buffer layer 112, the channel layer 113 having a compressive strain, and the barrier layer 114 having a tensile strain, and the spacer layer 115 having a compressive strain are laminated on a substrate 100 in this order. The gate insulating film 14 is arranged on the spacer layer 115. The gate electrode 15 is arranged on the gate insulating film 14. The source electrode 161 and the drain electrode 162 are electrically connected to the channel layer 113 directly or via another component.

摘要翻译： 本发明提供了能够实现高阈值电压和低通态电阻两者的场效应晶体管，其制造方法和电子器件。 在场效应晶体管中，由III族氮化物半导体形成缓冲层112，沟道层113，势垒层114和间隔层115，其上表面为III族 原子平面垂直于（0001）晶轴。 栅格弛豫缓冲层112，具有压缩应变的沟道层113和具有拉伸应变的阻挡层114以及具有压缩应变的间隔层115以此顺序层压在基板100上。 栅极绝缘膜14布置在间隔层115上。栅电极15布置在栅极绝缘膜14上。源极161和漏极162直接或经由另一个部件电连接到沟道层113。

公开(公告)号：US20130099245A1

公开(公告)日：2013-04-25

申请号：US13637316

申请日：2010-12-15

申请人： Yuji Ando ,  Takashi Inoue ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Kazuomi Endo

发明人： Yuji Ando ,  Takashi Inoue ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Kazuomi Endo

IPC分类号： H01L29/205 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/205 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/66431 ,  H01L29/7785 ,  H01L29/7787 ,  H01L29/78

摘要： The present invention provides a field effect transistor which can achieve both of a high threshold voltage and a low on-state resistance, a method for producing the same, and an electronic device. In the field effect transistor, each of a buffer layer 112, a channel layer 113, a barrier layer 114, and a spacer layer 115 is formed of a group-III nitride semiconductor, and each of the upper surfaces thereof is a group-III atomic plane that is perpendicular to a (0001) crystal axis. The lattice-relaxed buffer layer 112, the lattice-relaxed channel layer 113, and the barrier layer 114 having a tensile strain, and the spacer layer 115 are laminated on a substrate 100 in this order. The gate insulating film 14 is arranged on the spacer layer 115. The gate electrode 15 is arranged on the gate insulating film 14. The source electrode 161 and the drain electrode 162 are electrically connected to the channel layer 113 directly or via another component.

摘要翻译： 本发明提供了能够实现高阈值电压和低通态电阻两者的场效应晶体管，其制造方法和电子器件。 在场效应晶体管中，由III族氮化物半导体形成缓冲层112，沟道层113，势垒层114和间隔层115，其上表面为III族 原子平面垂直于（0001）晶轴。 晶格弛豫缓冲层112，晶格松弛沟道层113和具有拉伸应变的势垒层114和间隔层115依次层压在基板100上。 栅极绝缘膜14布置在间隔层115上。栅电极15布置在栅极绝缘膜14上。源极161和漏极162直接或经由另一个部件电连接到沟道层113。

公开(公告)号：US20120199889A1

公开(公告)日：2012-08-09

申请号：US13393002

申请日：2010-06-23

申请人： Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Kazuomi Endo

发明人： Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Kazuomi Endo

IPC分类号： H01L29/78

CPC分类号： H01L29/8122 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7809 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/8128

摘要： Provided is a semiconductor device in which the trade-off between the withstand voltage and the on-resistance is improved and the performance is increased.A semiconductor device comprises a substrate 1, a first n-type semiconductor layer 21′, a second n-type semiconductor layer 23, a p-type semiconductor layer 24, and a third n-type semiconductor layer 25′, wherein the first n-type semiconductor layer 21′, the second n-type semiconductor layer 23, the p-type semiconductor layer 24, and the third n-type semiconductor layer 25′ are laminated at the upper side of the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 21′ and the source electrode 12 is in ohmic-contact with the third n-type semiconductor layer 25′. A gate electrode 14 is arranged so as to fill an opening portion to be filled that extends from the third n-type semiconductor layer 25′ to the second n-type semiconductor layer 23, and the gate electrode 14 is in contact with the upper surface of the second n-type semiconductor layer 23, the side surfaces of the p-type semiconductor layer 24, and the side surfaces of the third n-type semiconductor layer 25′. The second n-type semiconductor layer 23 has composition that changes from the drain electrode 13 side toward the source electrode 12 side in the direction perpendicular to the plane of the substrate 1 and contains donor impurity.

摘要翻译： 提供一种半导体器件，其中耐压和导通电阻之间的折衷被提高并且性能提高。 半导体器件包括衬底1，第一n型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'，其中第一n型半导体层 型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'依次层叠在基板1的上侧。 漏电极13与第一n型半导体层21'欧姆接触，源电极12与第三n型半导体层25'欧姆接触。 栅电极14被布置成填充从第三n型半导体层25'延伸到第二n型半导体层23的待填充的开口部分，并且栅电极14与上表面 第二n型半导体层23，p型半导体层24的侧表面和第三n型半导体层25'的侧表面。 第二n型半导体层23具有从垂直于基板1的平面的方向从漏电极13侧向源电极12侧变化的成分，并且含有施主杂质。

公开(公告)号：US09154232B2

公开(公告)日：2015-10-06

申请号：US14112653

申请日：2011-12-09

申请人： Kazuomi Endo ,  Yoichi Hashimoto

发明人： Kazuomi Endo ,  Yoichi Hashimoto

IPC分类号： H04B10/06 ,  H04B10/61

CPC分类号： H04B10/6165 ,  H04B10/614

摘要： In order to allow reception in which receive sensitivity does not depend upon polarization state in reception of a multi-level phase optical signal, in this optical reception method, a multi-level phase optical signal of a single polarization is separated into a first optical signal and a second optical signal of which polarizations are mutually orthogonal, the ratio of the power of the first optical signal to the power of the second signal is calculated, and the difference between the phase of the first optical signal and the phase of second optical signal is calculated as an amount of compensation, whereupon, on the basis of the ratio and the amount of compensation, the first optical signal and the second optical signal are combined using a maximal ratio combining method, and the amount of compensation is modified on the basis of the ratio.

摘要翻译： 为了允许接收灵敏度不接收多级相位光信号的接收中的偏振状态的接收，在该光接收方法中，单极化的多电平相位光信号被分离为第一光信号 以及偏振相互正交的第二光信号，计算第一光信号的功率与第二信号的功率的比率，并且计算第一光信号的相位与第二光信号的相位之差 被计算为补偿量，因此，基于比率和补偿量，使用最大比组合方法组合第一光信号和第二光信号，并且基于该补偿量修改补偿量 的比例。

公开(公告)号：US20140044440A1

公开(公告)日：2014-02-13

申请号：US14112653

申请日：2011-12-09

申请人： Kazuomi Endo ,  Yoichi Hashimoto

发明人： Kazuomi Endo ,  Yoichi Hashimoto

IPC分类号： H04B10/61

CPC分类号： H04B10/6165 ,  H04B10/614

摘要： In order to allow reception in which receive sensitivity does not depend upon polarization state in reception of a multi-level phase optical signal, in this optical reception method, a multi-level phase optical signal of a single polarization is separated into a first optical signal and a second optical signal of which polarizations are mutually orthogonal, the ratio of the power of the first optical signal to the power of the second signal is calculated, and the difference between the phase of the first optical signal and the phase of second optical signal is calculated as an amount of compensation, whereupon, on the basis of the ratio and the amount of compensation, the first optical signal and the second optical signal are combined using a maximal ratio combining method, and the amount of compensation is modified on the basis of the ratio.

摘要翻译： 为了允许接收灵敏度不接收多级相位光信号的接收中的偏振状态的接收，在该光接收方法中，单极化的多电平相位光信号被分离为第一光信号 以及偏振相互正交的第二光信号，计算第一光信号的功率与第二信号的功率的比率，并且计算第一光信号的相位与第二光信号的相位之差 被计算为补偿量，因此，基于比率和补偿量，使用最大比组合方法组合第一光信号和第二光信号，并且基于该补偿量修改补偿量 的比例。

公开(公告)号：US08552471B2

公开(公告)日：2013-10-08

申请号：US13139789

申请日：2009-12-11

申请人： Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Kazuomi Endo

发明人： Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Kazuomi Endo

IPC分类号： H01L29/66

CPC分类号： H01L29/402 ,  H01L29/0619 ,  H01L29/2003 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7787

摘要： There is provided a semiconductor apparatus capable of achieving both a reverse blocking characteristic and a low on-resistance. The semiconductor apparatus includes a first semiconductor layer including a channel layer, a source electrode formed on the first semiconductor layer, a drain electrode formed at a distance from the source electrode on the first semiconductor layer, and a gate electrode formed between the source electrode and the drain electrode on the first semiconductor layer. The drain electrode includes a first drain region where reverse current between the first semiconductor layer and the first drain region is blocked, and a second drain region formed at a greater distance from the gate electrode than the first drain region, where a resistance between the first semiconductor layer and the second drain region is lower than a resistance between the first semiconductor layer and the first drain region.

摘要翻译： 提供了能够实现反向阻挡特性和低导通电阻的半导体装置。 半导体装置包括：第一半导体层，包括沟道层，形成在第一半导体层上的源电极，在第一半导体层上与源极间隔一定距离处形成的漏电极，以及形成在源电极和 第一半导体层上的漏电极。 漏电极包括第一漏极区，其中第一半导体层和第一漏极区之间的反向电流被阻挡，以及形成在比栅极电极比第一漏极区更远的距离处的第二漏区， 半导体层和第二漏极区域比第一半导体层和第一漏极区域之间的电阻低。

公开(公告)号：US20130113028A2

公开(公告)日：2013-05-09

申请号：US13393002

申请日：2010-06-23

申请人： Hironobu MIYAMOTO ,  Yasuhiro OKAMOTO ,  Yuji ANDO ,  Tatsuo NAKAYAMA ,  Takashi INOUE ,  Kazuki OTA ,  Kazuomi ENDO

发明人： Hironobu MIYAMOTO ,  Yasuhiro OKAMOTO ,  Yuji ANDO ,  Tatsuo NAKAYAMA ,  Takashi INOUE ,  Kazuki OTA ,  Kazuomi ENDO

IPC分类号： H01L29/78

CPC分类号： H01L29/8122 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/7809 ,  H01L29/7812 ,  H01L29/7813 ,  H01L29/8128

摘要： A semiconductor device comprises a substrate 1, a first n-type semiconductor layer 21′, a second n-type semiconductor layer 23, a p-type semiconductor layer 24, and a third n-type semiconductor layer 25′, wherein the first n-type semiconductor layer 21′, the second n-type semiconductor layer 23, the p-type semiconductor layer 24, and the third n-type semiconductor layer 25′ are laminated at the upper side of the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 21′ and the source electrode 12 is in ohmic-contact with the third n-type semiconductor layer 25′. A gate electrode 14 is arranged so as to fill an opening portion to be filled that extends from the third n-type semiconductor layer 25′ to the second n-type semiconductor layer 23, and the gate electrode 14 is in contact with the upper surface of the second n-type semiconductor layer 23, the side surfaces of the p-type semiconductor layer 24, and the side surfaces of the third n-type semiconductor layer 25′. The second n-type semiconductor layer 23 has composition that changes from the drain electrode 13 side toward the source electrode 12 side in the direction perpendicular to the plane of the substrate 1 and contains donor impurity.

摘要翻译： 半导体器件包括衬底1，第一n型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'，其中第一n型半导体层 型半导体层21'，第二n型半导体层23，p型半导体层24和第三n型半导体层25'依次层叠在基板1的上侧。 漏电极13与第一n型半导体层21'欧姆接触，源电极12与第三n型半导体层25'欧姆接触。 栅电极14被布置成填充从第三n型半导体层25'延伸到第二n型半导体层23的待填充的开口部分，并且栅电极14与上表面 第二n型半导体层23，p型半导体层24的侧表面和第三n型半导体层25'的侧表面。 第二n型半导体层23具有从垂直于基板1的平面的方向从漏电极13侧向源电极12侧变化的成分，并且含有施主杂质。