公开(公告)号：US20050112889A1

公开(公告)日：2005-05-26

申请号：US11024199

申请日：2004-12-29

申请人： Junichi Inoue ,  Teruo Asakawa ,  Kazuhiko Sugiyama

发明人： Junichi Inoue ,  Teruo Asakawa ,  Kazuhiko Sugiyama

IPC分类号： C23C14/56 ,  C23C16/54 ,  H01L21/00 ,  H01L21/04 ,  H01L21/66 ,  G01R31/26 ,  H01L21/76 ,  H01L21/302 ,  H01L21/461

CPC分类号： H01L21/67225 ,  C23C14/56 ,  C23C16/54 ,  H01L21/0405 ,  H01L21/67161 ,  H01L21/67173

摘要： The present invention provides a semiconductor device manufacturing line for applying a series of processes on a semiconductor substrate, and forming an integrated circuit on the semiconductor substrate by employing a semiconductor wafer having a diameter of 6 inches (150±3 mm: SEAJ specification) or less for the semiconductor substrate. This manufacturing line comprises two sub-lines conforming to the same specifications, each of these sub-lines is composed of a series of processing units including a film forming unit, a pattern exposure unit, an etching unit, and a test unit. In at least one pattern exposure unit and one etching unit, fine processing of 0.3 μm or less can be performed.

摘要翻译： 本发明提供了一种用于在半导体衬底上施加一系列工艺的半导体器件制造线，并且通过采用直径为6英寸（150±3mm：SEAJ规格）的半导体晶片或半导体衬底上形成集成电路， 较少用于半导体衬底。 该制造线包括符合相同规格的两条子线，这些子线中的每一条由包括成膜单元，图案曝光单元，蚀刻单元和测试单元的一系列处理单元组成。 在至少一个图案曝光单元和一个蚀刻单元中，可以执行0.3μm或更小的精细处理。

公开(公告)号：US4555650A

公开(公告)日：1985-11-26

申请号：US481737

申请日：1983-04-04

申请人： Teruo Asakawa

发明人： Teruo Asakawa

IPC分类号： H01L21/68 ,  G03F7/20 ,  H02K41/02 ,  H02K41/00

CPC分类号： G03F7/70716 ,  G03F7/70758 ,  H02K41/031 ,  H02K2201/18

摘要： A device for positioning a semiconductor substrate is provided comprising magnetic field group formed from a plurality of magnetic fields disposed on a plane in a two-dimensional array. The magnetic fields are provided with a perpendicular orientation relative to the plane and adjacent magnetic fields are directed in alternate directions. Coil sets are formed of a plurality of coils, the coils having a specific dimensional relationship with the magnetic field array. Coil groups are formed by fixedly securing a plurality of these coil sets to each other the coil groups being disposed within the magnetic field group so as to be freely movable along the plane. Electric current is applied to the coils which generates a force in each coil set so as to move the coil set in either one of the longitudinal and lateral directions of the array of magnetic fields, whereby a current-motion converter and a driving device making use of the converter can be formed.

摘要翻译： 提供一种用于定位半导体衬底的装置，包括由设置在二维阵列的平面上的多个磁场形成的磁场组。 磁场相对于平面具有垂直定向，并且相邻的磁场沿着交替的方向被引导。 线圈组由多个线圈形成，线圈与磁场阵列具有特定的尺寸关系。 线圈组通过将多个这些线圈组彼此固定地固定而形成，线圈组被布置在磁场组内，以便能够沿着平面自由移动。 对线圈施加电流，在每个线圈组中产生力，以使线圈组沿磁场阵列的纵向和横向方向移动，由此使电流运动转换器和使用的驱动装置 的转换器。

公开(公告)号：US4476420A

公开(公告)日：1984-10-09

申请号：US443471

申请日：1982-11-22

申请人： Teruo Asakawa

发明人： Teruo Asakawa

IPC分类号： G01D5/244 ,  G01D5/245 ,  G05B19/39 ,  G05D3/12 ,  G05B1/01

CPC分类号： G05B19/39 ,  G05D3/121

摘要： Positioning of a movable body can be achieved at a high resolution by making use of two position signals generated by a position detector, whose magnitudes are sinusoidal functions having different phases of the position of the movable body. On the basis of the two sinusoidal position signals, two bi-level digital position signals having different phase from each other are derived, and digital control for movement of the movable body is effected by making use of these two bi-level digital position signals until the movable body is brought into the proximity of a desired position. Thereafter, control is switched from the digital control to analog control for movement of the movable body, in which a position signal whose manitude is a sinusoidal function of the position of the movable body and has a zero-cross point at the desired position is used as a reference position signal. This reference position signal can be synthesized from the two position signals generated by the position detector by means of a simple signal synthesizer circuit according to the present invention. The signal synthesizer circuit comprises two multiplier type digital-analog converters, each of which is applied with a digital input signal and an analog input signal such as, for example, the above-mentioned sinusoidal position signal generated by the position detector and generates an analog output signal that is product including an algebraic sign of the digital input signal and the analog input signal, and an adder having the respective analog output signals of the two multiplier type digital-analog converters applied to its input. By appropriately selecting the digital values of the digital input signals, a desired reference position signal can be derived at the output of the adder.

摘要翻译： 可以通过利用由位置检测器产生的两个位置信号以高分辨率来实现移动体的定位，位置检测器的大小是具有不同移动体位置的正弦函数。 基于两个正弦位置信号，导出具有彼此不同相位的两个双电平数字位置信号，并且通过利用这两个双电平数字位置信号来实现移动体的移动的数字控制，直到 可移动体被带到所需位置附近。 此后，将控制从数字控制切换到可移动体的运动的模拟控制，其中使用其位置信号，其位置信号是可移动体的位置的正弦函数并且在期望位置处具有零交叉点 作为参考位置信号。 可以通过根据本发明的简单信号合成器电路由位置检测器产生的两个位置信号来合成该参考位置信号。 信号合成器电路包括两个乘法器型数模转换器，每个转换器应用数字输入信号和模拟输入信号，例如由位置检测器产生的上述正弦位置信号，并产生模拟 输出信号，其是包括数字输入信号和模拟输入信号的代数符号的乘积，以及加法器，其具有应用于其输入的两个乘法器型数模转换器的相应模拟输出信号。 通过适当地选择数字输入信号的数字值，可以在加法器的输出端导出期望的参考位置信号。

公开(公告)号：US07566665B2

公开(公告)日：2009-07-28

申请号：US11024199

申请日：2004-12-29

申请人： Junichi Inoue ,  Teruo Asakawa ,  Kazuhiko Sugiyama

发明人： Junichi Inoue ,  Teruo Asakawa ,  Kazuhiko Sugiyama

IPC分类号： H01L21/302

CPC分类号： H01L21/67225 ,  C23C14/56 ,  C23C16/54 ,  H01L21/0405 ,  H01L21/67161 ,  H01L21/67173

摘要： The present invention provides a semiconductor device manufacturing line for applying a series of processes on a semiconductor substrate, and forming an integrated circuit on the semiconductor substrate by employing a semiconductor wafer having a diameter of 6 inches (150±3 mm: SEAJ specification) or less for the semiconductor substrate. This manufacturing line comprises two sub-lines conforming to the same specifications, each of these sub-lines is composed of a series of processing units including a film forming unit, a pattern exposure unit, an etching unit, and a test unit. In at least one pattern exposure unit and one etching unit, fine processing of 0.3 μm or less can be performed.

摘要翻译： 本发明提供了一种用于在半导体衬底上施加一系列工艺的半导体器件制造线，并且通过采用直径为6英寸（150±3mm：SEAJ规格）的半导体晶片或半导体衬底上形成集成电路， 较少用于半导体衬底。 该制造线包括符合相同规格的两条子线，这些子线中的每一条由包括成膜单元，图案曝光单元，蚀刻单元和测试单元的一系列处理单元组成。 在至少一个图案曝光单元和一个蚀刻单元中，可以执行0.3μm或更小的精细处理。

公开(公告)号：US20090016859A1

公开(公告)日：2009-01-15

申请号：US11666163

申请日：2005-10-25

申请人： Teruo Asakawa

发明人： Teruo Asakawa

IPC分类号： B65H1/00

CPC分类号： H01L21/67727 ,  H01L21/67736 ,  H01L21/67775

摘要： A carrying system 1 has a carrying path which is laid out in such a manner as to pass through the lower sides of loading table 11 and the like provided at the front face side of treating devices 10, 100, 200, and covered by a cover 5. As the carrying path is positioned below the loading tables, the occupying areas of the loading table 11 and the like and portions of the region of the carrying path are shared so that space saving is achieved, and the accessibility to the treating device 10, 100 or the like from the front side thereof is improved, thereby realizing a layout which facilitates maintenance. A loading surface 11d or the like of the loading table 11 is set to a height which allows a conventional overhead-type carrying system 2 and unmanned carrying vehicle 3 of a floor-type carrying system to load an object on the loading surface, thereby ensuring the co-existence with the other carrying systems.

摘要翻译： 携带系统1具有输送路径，其布置成穿过设置在处理装置10,100,200的前表面处的装载台11等的下侧，并被盖 当承载路径位于装载台下方时，承载台11等的占有区域和运送路径的区域的部分被共享，从而实现节省空间，并且可处理装置10 ，100等从前侧提高，从而实现有利于维护的布局。 装载台11的装载面11d等被设定为允许地板式承载系统的常规塔式运载系统2和无人运载车辆3在装载面上装载物体的高度，从而确保 与其他携带系统的共存。

公开(公告)号：US06841485B1

公开(公告)日：2005-01-11

申请号：US09958970

申请日：2000-04-11

申请人： Junichi Inoue ,  Teruo Asakawa ,  Kazuhiko Sugiyama

发明人： Junichi Inoue ,  Teruo Asakawa ,  Kazuhiko Sugiyama

IPC分类号： C23C14/56 ,  C23C16/54 ,  H01L21/00 ,  H01L21/04 ,  H01L21/302

CPC分类号： H01L21/67225 ,  C23C14/56 ,  C23C16/54 ,  H01L21/0405 ,  H01L21/67161 ,  H01L21/67173

摘要： The present invention provides a semiconductor device manufacturing line for applying a series of processes on a semiconductor substrate, and forming an integrated circuit on the semiconductor substrate by employing a semiconductor wafer having a diameter of 6 inches (150±3 mm: SEAJ specification) or less for the semiconductor substrate. This manufacturing line comprises two sub-lines conforming to the same specifications, each of these sub-lines is composed of a series of processing units including a film forming unit, a pattern exposure unit, an etching unit, and a test unit. In at least one pattern exposure unit and one etching unit, fine processing of 0.3 μm or less can be performed.

摘要翻译： 本发明提供了一种用于在半导体衬底上施加一系列工艺的半导体器件制造线，并且通过采用直径为6英寸（150±3mm：SEAJ规格）的半导体晶片或半导体衬底上形成集成电路， 较少用于半导体衬底。 该制造线包括符合相同规格的两条子线，这些子线中的每一条由包括成膜单元，图案曝光单元，蚀刻单元和测试单元的一系列处理单元组成。 在至少一个图案曝光单元和一个蚀刻单元中，可以执行0.3μm或更小的精细处理。

公开(公告)号：US5374147A

公开(公告)日：1994-12-20

申请号：US942841

申请日：1992-09-10

申请人： Tsutomu Hiroki ,  Teruo Asakawa

发明人： Tsutomu Hiroki ,  Teruo Asakawa

IPC分类号： B65G49/07 ,  H01L21/687 ,  B65G47/24

CPC分类号： H01L21/68707 ,  Y10S414/136

摘要： A device for transferring a LCD substrate under a reduced pressure atmosphere comprises a first stage on which the LCD substrate is mounted such that the surface of the LCD substrate is substantially horizontal, a multi-joint arm mechanism for mounting the LCD substrate on a second stage of a delivery position after moving the first stage in substantially horizontal plane, a mechanism for pushing the LCD substrate on the first and second stages, and for positioning the LCD substrate at a home position.

摘要翻译： 用于在减压气氛下转移LCD基板的装置包括：第一阶段，LCD基板被安装在其上，使得LCD基板的表面基本上水平;多关节臂机构，用于将LCD基板安装在第二台上 在基本水平的平面中移动第一级之后的输送位置，用于在第一和第二级上推动LCD基板并将LCD基板定位在原始位置的机构。

公开(公告)号：US5248886A

公开(公告)日：1993-09-28

申请号：US842421

申请日：1992-02-27

申请人： Teruo Asakawa ,  Tetsu Osawa ,  Noboru Hosaka

发明人： Teruo Asakawa ,  Tetsu Osawa ,  Noboru Hosaka

IPC分类号： B65G49/00 ,  C23C14/56 ,  C30B35/00 ,  H01J37/317 ,  H01L21/00 ,  H01L21/265 ,  H01L21/677

CPC分类号： H01L21/67069 ,  C30B35/005 ,  H01L21/67201 ,  H01L21/67213 ,  H01L21/67259 ,  H01L21/67745

摘要： Load lock chambers having a function of detecting positional deviation of wafers are provided in a process chamber of an ion injection apparatus, two on a carrying-in side, and two on a carrying-out side. One load lock chamber on the carrying-in side and one on the carrying-out side are used as a standby. Carrying-in carrying-out members and are outside of the process chamber. Two transfer members are in the process chamber. A dummy wafer stage is formed at a position which can be accessed by the transfer members. Wafers are transferred from load stages by the carrying-in member via the load lock chambers to the process chamber through a double operation line. Loading a wafer on the turn table and unloading a wafer therefrom can be performed simultaneously by operations of the transfer members and. The wafers are similarly carried out of the apparatus in a double operation line. At this time, dummy wafers in the process chamber can be used, if necessary.

公开(公告)号：US5064337A

公开(公告)日：1991-11-12

申请号：US552852

申请日：1990-07-12

申请人： Teruo Asakawa ,  Tetsu Ohsawa

发明人： Teruo Asakawa ,  Tetsu Ohsawa

IPC分类号： H01L21/677

CPC分类号： H01L21/67769 ,  Y10S414/14

摘要： A handling apparatus, used for handling a carrier of semiconductor wafers, comprises a first mechanism for transferring a carrier between a loader/unloader table and a storage compartment, and a second mechanism, for moving the first mechanism in both vertical and horizontal directions. The first mechanism includes an arm, a loading portion for loading the carrier, and an arm-rocking mechanism. The second mechanism moves the first mechanism to the loader/unloader table, picks up the carrier, and then moves the first mechanism to the storage compartment, where the arm is rocked, so as to discharge the object from the loading portion.

摘要翻译： 用于处理半导体晶片的载体的处理装置包括用于在装载机/卸载台和存储室之间传送载体的第一机构和用于在垂直和水平方向上移动第一机构的第二机构。 第一机构包括臂，用于装载托架的装载部分和臂摆动机构。 第二机构将第一机构移动到装载机/卸载机台，拾取载体，然后将第一机构移动到臂被摇动的储藏室，以将物体从装载部分排出。

公开(公告)号：US20050260824A1

公开(公告)日：2005-11-24

申请号：US11189700

申请日：2005-07-27

申请人： Junichi Inoue ,  Teruo Asakawa ,  Kazuhiko Sugiyama

发明人： Junichi Inoue ,  Teruo Asakawa ,  Kazuhiko Sugiyama

IPC分类号： C23C14/56 ,  C23C16/54 ,  H01L21/00 ,  H01L21/04 ,  H01L21/76

CPC分类号： H01L21/67225 ,  C23C14/56 ,  C23C16/54 ,  H01L21/0405 ,  H01L21/67161 ,  H01L21/67173

摘要： The present invention provides a semiconductor device manufacturing line for applying a series of processes on a semiconductor substrate, and forming an integrated circuit on the semiconductor substrate by employing a semiconductor wafer having a diameter of 6 inches (150±3 mm: SEAJ specification) or less for the semiconductor substrate. This manufacturing line comprises two sub-lines conforming to the same specifications, each of these sub-lines is composed of a series of processing units including a film forming unit, a pattern exposure unit, an etching unit, and a test unit. In at least one pattern exposure unit and one etching unit, fine processing of 0.3 μm or less can be performed.