公开(公告)号：US11356086B2

公开(公告)日：2022-06-07

申请号：US17163894

申请日：2021-02-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Huanzhang Huang ,  Amit Rane

IPC: G06F13/38 ,  H03K17/00 ,  H03K19/003 ,  H03K17/56

Abstract: Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.

公开(公告)号：US11010319B2

公开(公告)日：2021-05-18

申请号：US15931762

申请日：2020-05-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Win Naing Maung ,  Bhupendra Sharma ,  Huanzhang Huang ,  Douglas Edward Wente ,  Suzanne Mary Vining ,  Mustafa Ulvi Erdogan

IPC: H03K5/24 ,  G06F13/38 ,  H03F3/45 ,  G06F13/42

Abstract: Aspects of the disclosure provide for a method. In at least some examples, the method includes receiving, at a circuit, data via a differential input signal. The method further includes detecting a falling edge in the data received via the differential input signal. The method further includes holding an output of the circuit at a final logical value of the data. The method further includes disabling a transmitter of the circuit while holding the output of the circuit at the final logical value of the data. The method further includes releasing the output of the circuit from the final logical value of the data.

公开(公告)号：US10782717B1

公开(公告)日：2020-09-22

申请号：US16656742

申请日：2019-10-18

Applicant: Texas Instruments Incorporated

Inventor： Jikai Chen ,  Yonghui Tang ,  Yuan Rao ,  Huanzhang Huang ,  Yanli Fan

IPC: G05F1/56 ,  H02M3/158 ,  H03K3/013 ,  H04B1/16 ,  H04B1/12

Abstract: A jitter compensation circuit operates in a first conduction state responsive to a high-to low transition of data and a low-to-high transition of data. The circuit operates in a second conduction state when there is no transition of data. The circuit compensates charge to a voltage supply in the first conduction state, thereby reducing voltage drop caused by transition of data.

公开(公告)号：US10657090B2

公开(公告)日：2020-05-19

申请号：US16716891

申请日：2019-12-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Win Naing Maung ,  Bhupendra Sharma ,  Huanzhang Huang ,  Douglas Edward Wente ,  Suzanne Mary Vining ,  Mustafa Ulvi Erdogan

IPC: H03K5/24 ,  G06F13/38 ,  H03F3/45 ,  G06F13/42

Abstract: Aspects of the disclosure provide for a method. In at least some examples, the method includes receiving, at a circuit, data via a differential input signal. The method further includes detecting a falling edge in the data received via the differential input signal. The method further includes holding an output of the circuit at a final logical value of the data. The method further includes disabling a transmitter of the circuit while holding the output of the circuit at the final logical value of the data. The method further includes releasing the output of the circuit from the final logical value of the data.

公开(公告)号：US09602318B2

公开(公告)日：2017-03-21

申请号：US14819239

申请日：2015-08-05

Applicant: Texas Instruments Incorporated

Inventor： Roland Sperlich ,  Huanzhang Huang ,  Charles M. Branch

IPC: H03H7/30 ,  H04L27/01 ,  H04L25/03 ,  H04L25/02 ,  H04B3/14

CPC classification number: H04L27/01 ,  H04B3/144 ,  H04L25/026 ,  H04L25/03019 ,  H04L25/03885

Abstract: A serial communication circuit (FIG. 3) is disclosed. The circuit includes an equalizer circuit (306) arranged to receive a data signal (CH 1) and produce an equalized data signal. A log detector circuit (300) receives the data signal and produces a power signal indicating a power level of the data signal. A decision circuit (332) receives the power signal and produces a select signal. A first selection circuit (336) receives a plurality of first correction signals and applies one of the first correction signals to the equalizer circuit in response to the select signal.

公开(公告)号：US20140159814A1

公开(公告)日：2014-06-12

申请号：US14048750

申请日：2013-10-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Weicheng Zhang ,  Huanzhang Huang ,  Yanli Fan ,  Mark W. Morgan

IPC: H03F3/45

CPC classification number: H03F3/45219 ,  H03F3/45632 ,  H03F2203/45466 ,  H03F2203/45646 ,  H03F2203/45648

Abstract: A differential receiver with reduced common mode induced propagation delay variance. One implementation of a differential receiver includes a first differential amplifier, a second differential amplifier, and a first current source. The first differential amplifier includes a first transistor pair. The second differential amplifier includes a second transistor pair. The first current source is coupled to a drain node of a first transistor of the first transistor pair. The first current source is configured to generate a variable first current at the drain node as of function of a sum of a variable tail current of the first differential amplifier and a variable tail current of the second differential amplifier.

Abstract translation: 具有降低的共模感应传播延迟方差的差分接收机。 差分接收机的一个实施方式包括第一差分放大器，第二差分放大器和第一电流源。 第一差分放大器包括第一晶体管对。 第二差分放大器包括第二晶体管对。 第一电流源耦合到第一晶体管对的第一晶体管的漏极节点。 第一电流源被配置为根据第一差分放大器的可变尾电流和第二差分放大器的可变尾电流的和的函数，在漏极节点处产生可变的第一电流。