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公开(公告)号：US11569827B1
公开(公告)日：2023-01-31
申请号：US17390362
申请日：2021-07-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sthanunathan Ramakrishnan , Nithin Gopinath , Sai Aditya Nurani , Joseph Palackal Mathew , Nagalinga Swamy Basayya Aremallapur
Abstract: Aspects of the description provide for an analog-to-digital converter (ADC) operable to convert an analog input signal to an output signal at an output of the ADC. In some examples, the ADC includes multiple sub-ADCs coupled in parallel, each of the multiple sub-ADCs coupled to the output of the ADC and operable to receive the analog input signal. The ADC is configured to operate the sub-ADCs in a consecutive operation loop including a transition phase in which the ADC operates each of the sub-ADCs sequentially for a first number of sequences, an estimation phase in which the ADC operates each of the sub-ADCs sequentially for a second number of sequences following the first number of sequences, and a randomization phase in which the ADC operates subsets of the sub-ADCs for a third number of sequences following the second number of sequences.
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公开(公告)号：US10050636B2
公开(公告)日：2018-08-14
申请号：US15389236
申请日：2016-12-22
Applicant: Texas Instruments Incorporated
Inventor： Jawaharlal Tangudu , Sthanunathan Ramakrishnan , Nagarajan Viswanathan , Pooja Sundar
Abstract: Methods and apparatus for reducing non-linearity in analog to digital converters are disclosed. An example apparatus includes an analog-to-digital converter to convert an analog signal into a digital signal; and a non-linearity corrector coupled to the analog-to-digital converter to determine a derivative of the digital signal; determine cross terms including a combination of the digital signal and the derivative of the digital signal; and determine a non-linearity term corresponding to a combination of the cross terms.
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公开(公告)号：US20180019732A1
公开(公告)日：2018-01-18
申请号：US15645647
申请日：2017-07-10
Applicant: Texas Instruments Incorporated
Inventor： Jaiganesh Balakrishnan , Sthanunathan Ramakrishnan , Pooja Sundar , Sashidharan Venkatraman
CPC classification number: H03H17/0219 , G06F5/01 , G06F7/5443 , H03H17/0045 , H03H17/06 , H03M1/0626 , H03M1/12 , H03M1/1215
Abstract: In accordance with an example, an integrated circuit includes a linear combiner having an input for receiving a signal. The linear combiner also has a plurality of operator circuits for applying weighting factors to the signal, in which a first operator circuit in the plurality of operator circuits performs a first operation on the signal using a first sub-weight of one of the weighting factors to provide a first tile output and a second operator circuit in the plurality of operator circuits performs a second operation on the signal using a second sub-weight of the one of the weighting factors to provide a second tile output. The linear combiner also has an adder having a first input coupled to receive the first tile output and the second tile outputs and providing a combined output.
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公开(公告)号：US20150249907A1
公开(公告)日：2015-09-03
申请号：US14194449
申请日：2014-02-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Pankaj Gupta , Sthanunathan Ramakrishnan , Jaiganesh Balakrishnan , Sachin Bhardwaj
IPC: H04W4/04
CPC classification number: H04W4/043
Abstract: Several systems and methods for location estimation in a multi-floor environment are disclosed. In an embodiment, the method includes performing wireless scanning so as to receive wireless signals from one or more access points from among a plurality of access points positioned at plurality of locations, respectively at one or more floors from among a plurality of floors within the multi-floor environment. A first set of RSSI measurements is computed corresponding to the wireless signals. Absolute floor location information is determined based on the first set of RSSI measurements and a pre-defined objective function. The pre-defined objective function is configured to maximize a probability of a user being located at a floor so as to receive the wireless signals. A user floor location is determined based on the absolute floor location information. The user location is estimated at least in part based on the user floor location.
Abstract translation: 公开了用于多层环境中的位置估计的几种系统和方法。 在一个实施例中，该方法包括执行无线扫描，以便从位于多个接入点内的多个接入点中的多个接入点接收无线信号，所述多个接入点分别位于多个接入点内的多个接入点 - 地板环境。 对应于无线信号计算第一组RSSI测量。 基于第一组RSSI测量和预定义的目标函数来确定绝对楼层位置信息。 预定义的目标函数被配置为最大化用户位于楼层的概率以便接收无线信号。 基于绝对楼层位置信息确定用户楼层位置。 至少部分地基于用户楼层位置来估计用户位置。
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公开(公告)号：US20140005751A1
公开(公告)日：2014-01-02
申请号：US14019113
申请日：2013-09-05
Applicant: Texas Instruments Incorporated
Inventor： Sthanunathan Ramakrishnan , Jaiganesh Balakrishnan
IPC: A61N1/372
CPC classification number: A61N1/37252 , A61N1/08 , A61N1/37211
Abstract: By a medical implant transceiver implantable within a body of a living organism, a portion of a signal is received from a medical controller transceiver external to the body of the living organism. Based on directions within the portion of the signal, a time duration is determined, after which a subsequent portion of the signal is to be transmitted from the medical controller transceiver. The directions include a value indicative of the time duration. The time duration differs based on the value. The subsequent portion is to be transmitted from the medical controller transceiver after an end of the portion. The medical implant transceiver enters into an inactive state for the time duration and awakens after the time duration has elapsed.
Abstract translation: 通过可植入在活体内的医疗植入物收发器，信号的一部分从生物体的身体外部的医疗控制收发器接收。 基于信号部分内的方向，确定持续时间，之后从医疗控制收发器发送信号的后续部分。 方向包括指示持续时间的值。 持续时间根据值而不同。 在部分结束之后，将从医疗控制器收发器发送随后的部分。 医疗植入物收发器在持续时间内进入非活动状态，并在持续时间过去后唤醒。
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Patent Agency Ranking
公开(公告)号：US11777513B2
公开(公告)日：2023-10-03
申请号：US17538746
申请日：2021-11-30
Applicant: Texas Instruments Incorporated
Inventor： Karthikeyan Gunasekaran , Snehasish Roychowdhury , Rakesh Manjunath , Aswath V S , Sthanunathan Ramakrishnan , Sarma Sudareswara Gunturi , Rahul Sharma , Jagannathan Venkataraman , Nagarajan Viswanathan
CPC classification number: H03M1/1033 , H03M1/0631 , H03M1/0863 , H03M1/662
Abstract: A spur correction system for a transmit chain having an interleaving multiplexer. In some embodiments, the spur correction system includes a spur sense chain, a correction controller, and a Q path corrector. The interleaving multiplexer combines signals from multiple bands in response to a clock signal. The spur sense chain estimates an error that is in phase with the clock signal (an I-phase error) and an error that is a derivative of the clock signal (a Q-phase error). The correction controller compensates for the estimated I-phase error by injecting an I-phase correction signal into the transmit chain. The Q path corrector compensates for the estimated Q-phase error by selectively connecting one or more capacitors within the interleaving multiplexer.
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公开(公告)号：US10979262B2
公开(公告)日：2021-04-13
申请号：US16902529
申请日：2020-06-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: IQ mismatch correction for analog chain IQ mismatch impairments is based on a two-filter architecture. In either RX or TX, an IQmc mismatch corrector (digital chain) filters I and Q digital signals, and includes an I-path to receive the I signal, and a Q-path to receive the Q signal, and is configured with two filters: an in-path filter to filter either the I signal or the Q signal received in the same path; and a cross-path filter to filter either the I signal or the Q signal received in the other path. The IQmc mismatch corrector can include: an I-path delay element to provide a delay to the I signal corresponding to a delay through either the in-path filter or the cross-path filter; and a Q-path delay element to provide a delay to the Q signal corresponding to a delay through either the in-path filter or the cross-path filter.
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公开(公告)号：US10250273B2
公开(公告)日：2019-04-02
申请号：US15791538
申请日：2017-10-24
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sthanunathan Ramakrishnan , Sashidharan Venkatraman , Chandrasekhar Sriram , Jawaharlal Tangudu
Abstract: An integrated circuit chip includes an interleaved analog-to-digital converter (ADC) and an interleaving calibration circuit. The interleaved ADC includes a plurality of ADCs that are each configured to sample an analog signal. The interleaved ADC is configured to convert the analog signal into an interleaved analog-to-digital signal (IADC signal) that includes a plurality of spurious signals formed from mismatches between the plurality of ADCs. The interleaving calibration circuit is configured to receive the IADC signal from the interleaved ADC, generate a mismatch profile estimate corresponding to the plurality of spurious signals to generate one or more mismatch profile estimates, determine whether a first mismatch profile estimate is in a frequency band of interest, and, in response to a determination that the first mismatch profile estimate is in the frequency band of interest, generate a set of model parameters based on the first mismatch profile estimate.
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公开(公告)号：US09813072B2
公开(公告)日：2017-11-07
申请号：US15145375
申请日：2016-05-03
Applicant: TEXAS INSTRUMENTS INCORPORATED
CPC classification number: H03M1/0626 , H03M1/1009 , H03M1/1215
Abstract: Methods, apparatus, systems and articles of manufacture to increase an integrity of mismatch corrections in an interleaved analog to digital converter are disclosed. An example apparatus includes an instantaneous mismatch estimator that uses an output of an interleaved analog to digital converter to identify a mismatch estimate between two or more component analog to digital converters of the interleaved analog to digital converter. An integrity monitor is to cause the instantaneous mismatch estimator to avoid incorrectly providing the mismatch estimate to a filter, the integrity monitor to instruct the filter to remove the mismatch estimate when the mismatch estimate is detected to be inaccurate.
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30.发明授权公开(公告)号：US09762254B2
公开(公告)日：2017-09-12
申请号：US15230643
申请日：2016-08-08
Applicant: TEXAS INSTRUMENTS INCORPORATED
CPC classification number: H03M1/0624 , H03M1/0626 , H03M1/1009 , H03M1/1215
Abstract: A system includes a first tracking filter configured to track a frequency domain mismatch profile between component analog-to-digital convertors (ADCs) of an interleaved ADC (IADC), and a second tracking filter configured to a track a frequency independent timing delay mismatch and a timing delay mismatch correction error based on frequency domain mismatch profile estimates. An output of the first tracking filter determines a correction of a frequency dependent mismatch profile in an output of the interleaved ADC and an output of the second tracking filter determines a correction of the timing delay mismatch correction error in the output of the interleaved ADC.
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