公开(公告)号：US20060126408A1

公开(公告)日：2006-06-15

申请号：US11283072

申请日：2005-11-21

申请人： Thorsten Bucksch

发明人： Thorsten Bucksch

IPC分类号： G11C29/00

CPC分类号： G11C29/44 ,  G11C5/04 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/109 ,  G11C11/401 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/48 ,  G11C29/846 ,  G11C2029/1208

摘要： The invention relates to a memory buffer, a method for operating the memory buffer, a memory module with a memory buffer, a testing method for the memory module, and an operating method for the memory module. The memory buffer comprises at least one memory logic unit that is connected with at least one memory-side bus system and with at least one host-side bus system, and that is characterized in that at least one redundancy memory is further available, so that a comparison of at least one memory cell address of said memory logic unit with at least one further memory cell address can be performed, and a transmission of at least one bus signal can be switched between said memory-side bus system and said redundancy memory on the basis of the comparison.

摘要翻译： 本发明涉及一种存储器缓冲器，一种用于操作存储器缓冲器的方法，具有存储器缓冲器的存储器模块，用于存储器模块的测试方法以及用于存储器模块的操作方法。 存储器缓冲器包括至少一个存储器逻辑单元，其与至少一个存储器侧总线系统和至少一个主机侧总线系统连接，并且其特征在于至少一个冗余存储器可用，使得 可以执行所述存储器逻辑单元的至少一个存储器单元地址与至少一个另外的存储器单元地址的比较，并且可以在所述存储器侧总线系统和所述冗余存储器之间切换至少一个总线信号的传输 比较的基础。

公开(公告)号：US20050200372A1

公开(公告)日：2005-09-15

申请号：US11065896

申请日：2005-02-25

申请人： Thorsten Bucksch

发明人： Thorsten Bucksch

IPC分类号： G01R31/02 ,  G01R31/28 ,  G01R35/00 ,  H01L21/66

CPC分类号： G01R31/2889

摘要： One embodiment of the invention provides a standardization module for use in standardizing tester channels of a tester unit using a standardization unit for making contact with contact faces which are connected to the tester channels and for standardizing the tester channels. The standardization module has a first surface on which first contact faces are arranged in such a way that contact can be made by a contact making card of the tester unit with the first contact faces in a defined fashion. The standardization module has a second surface on which second contact faces are arranged in such a way that contact can be made with the second contact faces using the standardization unit. Each of the first contact faces is respectively connected to one of the second contact faces.

摘要翻译： 本发明的一个实施例提供了一种用于使用标准化单元标准化测试器单元的测试仪通道的标准化模块，该标准化单元与连接到测试仪通道的接触面接触并标准化测试仪通道。 标准化模块具有第一表面，第一接触面以这样的方式布置，使得可以通过测试器单元的接触卡以限定的方式与第一接触面进行接触。 标准化模块具有第二表面，第二接触面以这样的方式布置，使得可以使用标准化单元与第二接触面进行接触。 每个第一接触面分别连接到第二接触面中的一个。

公开(公告)号：US07715257B2

公开(公告)日：2010-05-11

申请号：US11928790

申请日：2007-10-30

申请人： Thorsten Bucksch

发明人： Thorsten Bucksch

IPC分类号： G11C7/00

CPC分类号： G01R31/31717 ,  G01R31/3193 ,  G11C5/04 ,  G11C29/02 ,  G11C29/022 ,  G11C29/1201 ,  G11C29/50012

摘要： A test method and a semiconductor device is disclosed. One embodiment provides sending out a test signal by a semiconductor device. A reflected signal generated in reaction is compared to the test signal with a first threshold value. The reflected signal is compared with a second threshold value differing from the first threshold value.

摘要翻译： 公开了一种测试方法和半导体器件。 一个实施例提供了通过半导体器件发送测试信号。 将反应中产生的反射信号与具有第一阈值的测试信号进行比较。 将反射信号与不同于第一阈值的第二阈值进行比较。

公开(公告)号：US07415649B2

公开(公告)日：2008-08-19

申请号：US11253813

申请日：2005-10-20

申请人： Thorsten Bucksch

发明人： Thorsten Bucksch

IPC分类号： G01R31/28

CPC分类号： G11C29/56004 ,  G11C5/04 ,  G11C29/10 ,  G11C29/16 ,  G11C29/56

摘要： The invention relates to a semi-conductor component test procedure, as well as to a semi-conductor component test device with a shift register, which comprises several memory devices from which pseudo-random values (BLA, COL, ROW) to be used for testing a semi-conductor component are able to be tapped and emitted at corresponding outputs of the semi-conductor component test device, whereby the shift register comprises at least one further memory device, from which a further pseudo-random value (VAR) is able to be tapped and whereby a device is provided, with which the further pseudo-random value (VAR) can selectively, if needed, be emitted at at least one corresponding further output of the semi-conductor component test device.

摘要翻译： 本发明涉及半导体部件测试程序，以及具有移位寄存器的半导体部件测试装置，其包括若干存储器件，伪随机值（BLA，COL，ROW）用于 测试半导体部件能够在半导体部件测试装置的对应的输出处被抽头并发射，由此移位寄存器包括至少一个另外的存储器件，进一步的伪随机值（VAR） 被抽头并且由此提供一个装置，如果需要，另外的伪随机值（VAR）可以选择性地在半导体部件测试装置的至少一个对应的另外的输出端发射。

公开(公告)号：US06898739B2

公开(公告)日：2005-05-24

申请号：US10151989

申请日：2002-05-21

申请人： Thorsten Bucksch ,  Ralf Schneider

发明人： Thorsten Bucksch ,  Ralf Schneider

IPC分类号： G11C29/34 ,  G06F11/00

CPC分类号： G11C29/34 ,  G11C11/401

摘要： A method for testing a memory circuit selects each cell in a region of a cell array as a target cell and performs a test cycle which includes selecting the target cell and neighboring cells which contain at least those cells for which is cannot be ruled out that their operation causes a fault-producing interaction. A data item is written to the target cell in order to produce one of two defined states. A write signal is applied to the neighboring cells in order to produce an undefined state which lies between the two defined states. The target cell and the neighboring cells are then read and the result of the reading process is used to check whether there is any interaction between the operation of the target cell and the operation of the neighboring cells.

摘要翻译： 用于测试存储器电路的方法选择单元阵列的区域中的每个单元作为目标单元，并且执行测试周期，其包括选择目标单元和至少包含那些不能被排除的那些单元的相邻单元， 操作导致故障生成交互。 将数据项写入目标单元以产生两个定义状态之一。 写信号被施加到相邻的单元，以便产生位于两个定义状态之间的未定义状态。 然后读取目标单元和相邻单元，并且使用读取过程的结果来检查目标单元的操作与相邻单元的操作之间是否存在任何交互。

公开(公告)号：US20050024059A1

公开(公告)日：2005-02-03

申请号：US10878681

申请日：2004-06-29

申请人： Thorsten Bucksch ,  Arti Roth

发明人： Thorsten Bucksch ,  Arti Roth

IPC分类号： G01R31/319 ,  G04D7/00

CPC分类号： G01R31/3191

摘要： A process and device for calibrating a semiconductor component test system includes a first connection, at which a corresponding signal, in particular a calibration signal can be input, and a second and third connection, at which the signal, in particular a calibration signal, can be emitted. The first connection is and/or can be connected via a corresponding line to a first switching apparatus, which is and/or can be connected to the second connection. A second switching apparatus is and/or can be connected to the third connection. Advantageously, the signal is then transferred to the second connection, and barred from the third connection by the first switching apparatus being closed and the second switching apparatus being opened.

摘要翻译： 用于校准半导体部件测试系统的过程和设备包括第一连接，在该第一连接处可以输入相应的信号，特别是校准信号，以及第二和第三连接，在该第二连接处，信号，特别是校准信号可以在该连接 被排出。 第一连接和/或可以经由相应的线路连接到第一开关设备，第一开关设备是和/或可以连接到第二连接。 第二开关装置和/或可以连接到第三连接。 有利地，信号然后被传送到第二连接，并且被第一开关装置关闭并且第二开关装置打开的从第三连接被阻止。

公开(公告)号：US20090109774A1

公开(公告)日：2009-04-30

申请号：US11928790

申请日：2007-10-30

申请人： Thorsten Bucksch

发明人： Thorsten Bucksch

IPC分类号： G11C29/38

CPC分类号： G01R31/31717 ,  G01R31/3193 ,  G11C5/04 ,  G11C29/02 ,  G11C29/022 ,  G11C29/1201 ,  G11C29/50012

摘要： A test method and a semiconductor device is disclosed. One embodiment provides sending out a test signal by a semiconductor device. A reflected signal generated in reaction is compared to the test signal with a first threshold value. The reflected signal is compared with a second threshold value differing from the first threshold value.

摘要翻译： 公开了一种测试方法和半导体器件。 一个实施例提供了通过半导体器件发送测试信号。 将反应中产生的反射信号与具有第一阈值的测试信号进行比较。 将反射信号与不同于第一阈值的第二阈值进行比较。

公开(公告)号：US20060253756A1

公开(公告)日：2006-11-09

申请号：US11253813

申请日：2005-10-20

申请人： Thorsten Bucksch

发明人： Thorsten Bucksch

IPC分类号： G01R31/28

CPC分类号： G11C29/56004 ,  G11C5/04 ,  G11C29/10 ,  G11C29/16 ,  G11C29/56

摘要： The invention relates to a semi-conductor component test procedure, as well as to a semi-conductor component test device with a shift register, which comprises several memory devices from which pseudo-random values (BLA, COL, ROW) to be used for testing a semi-conductor component are able to be tapped and emitted at corresponding outputs of the semi-conductor component test device, whereby the shift register comprises at least one further memory device, from which a further pseudo-random value (VAR) is able to be tapped and whereby a device is provided, with which the further pseudo-random value (VAR) can selectively, if needed, be emitted at at least one corresponding further output of the semi-conductor component test device.

摘要翻译： 本发明涉及半导体部件测试程序，以及具有移位寄存器的半导体部件测试装置，其包括若干存储器件，伪随机值（BLA，COL，ROW）用于 测试半导体部件能够在半导体部件测试装置的对应的输出处被抽头并发射，由此移位寄存器包括至少一个另外的存储器件，进一步的伪随机值（VAR） 被抽头并且由此提供一个装置，如果需要，另外的伪随机值（VAR）可以选择性地在半导体部件测试装置的至少一个对应的另外的输出端发射。

公开(公告)号：US20050273679A1

公开(公告)日：2005-12-08

申请号：US11136714

申请日：2005-05-25

申请人： Thorsten Bucksch

发明人： Thorsten Bucksch

IPC分类号： G01R31/28 ,  G11C29/00 ,  G11C29/26 ,  G11C29/38 ,  G11C29/48

CPC分类号： G11C29/1201 ,  G11C29/26 ,  G11C29/38 ,  G11C29/48

摘要： The invention relates to a semi-conductor component test procedure for a system with several memory component modules, each comprising at least one memory component with a buffer connected in series before it, whereby a test module is used for testing, which test module comprises a buffer, not however a memory component corresponding with the memory components of the memory component modules. Furthermore the invention relates to a test module to be used during a corresponding procedure, in particular to a test module, which comprises a buffer, not however a memory component corresponding with the memory components of the memory component modules.

摘要翻译： 本发明涉及一种具有多个存储器组件模块的系统的半导体组件测试程序，每个存储器组件模块包括至少一个存储器组件，缓冲器在其之前串联连接，由此测试模块用于测试，该测试模块包括 缓冲区，而不是与存储器组件模块的存储器组件相对应的存储器组件。 此外，本发明涉及在相应过程期间使用的测试模块，特别是涉及一种测试模块，该测试模块包括缓冲器，而不是与存储器组件模块的存储器组件对应的存储器组件。

公开(公告)号：US20050162176A1

公开(公告)日：2005-07-28

申请号：US10995111

申请日：2004-11-24

申请人： Thorsten Bucksch

发明人： Thorsten Bucksch

IPC分类号： G01R31/28 ,  G01R31/319 ,  G11C29/00 ,  G11C29/48 ,  G11C29/56 ,  G01R31/02

CPC分类号： G01R31/31924 ,  G01R31/2889 ,  G01R31/31905 ,  G01R31/31926 ,  G11C29/006 ,  G11C29/48 ,  G11C29/56 ,  G11C2029/5602

摘要： The invention relates to a test device for testing digital semiconductor circuits at wafer level having a probe card which sends/receives digital test signals to/from a test head and distributes signal channels, carrying test signals, to the respective location on the wafer via an interposer. The interposer has a printed circuit board with contact pins on both sides, and a needle or contact stud card. Additionally, all signal channels in the test device or signal channels which carry time-critical test signals in the test device contain a respective signal amplifier, the signal amplifiers preferably being digital signal amplifiers which are mounted on the printed circuit board of the interposer.

摘要翻译： 本发明涉及一种用于测试晶片级数字半导体电路的测试装置，该测试装置具有向测试头发送/接收数字测试信号的探针卡，并将经由测试信号传送到晶片上的相应位置的信号通道经由 插入。 插入器具有印刷电路板，两面具有接触针，以及针或接触螺柱卡。 此外，测试装置中携带时间关键测试信号的测试装置或信号通道中的所有信道都包含相应的信号放大器，信号放大器最好是安装在插入器的印刷电路板上的数字信号放大器。