公开(公告)号：US5989970A

公开(公告)日：1999-11-23

申请号：US774796

申请日：1996-12-30

申请人： Makoto Ohkawa ,  Makio Iida ,  Mikimasa Suzuki

发明人： Makoto Ohkawa ,  Makio Iida ,  Mikimasa Suzuki

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/70

CPC分类号： H01L28/24

摘要： Even when a contact hole is formed before thin-film resistor formation, a contact area exposed in the contact hole is prevented from damaging. A semiconductor element is formed in a silicon semiconductor substrate and an oxide film is formed on the surface of the semiconductor substrate. Then, a contact hole is formed on the oxide film and moreover, a CrSiN film serving as a thin-film resistor and a TiW film serving as a barrier metal are formed on the oxide film. The TiW film is patterned by a mask and the CrSiN film is patterned through chemical dry etching. Finally, an Al electrode is formed on the semiconductor element and the CrSiN film through the contact hole and moreover a protective film is formed thereon.

摘要翻译： 即使在形成薄膜电阻器之前形成接触孔，也可以防止在接触孔中暴露的接触区域的损伤。 半导体元件形成在硅半导体衬底中，并且在半导体衬底的表面上形成氧化物膜。 然后，在氧化膜上形成接触孔，此外，在氧化膜上形成用作薄膜电阻器的CrSiN膜和用作阻挡金属的TiW膜。 通过掩模对TiW膜进行构图，并通过化学干蚀刻对CrSiN膜进行图案化。 最后，通过接触孔在半导体元件和CrSiN膜上形成Al电极，并且在其上形成保护膜。

公开(公告)号：US5747846A

公开(公告)日：1998-05-05

申请号：US346287

申请日：1994-11-23

申请人： Makio Iida ,  Tetsuo Fujii ,  Yoshihiko Isobe

发明人： Makio Iida ,  Tetsuo Fujii ,  Yoshihiko Isobe

IPC分类号： H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L27/10

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11531

摘要： A non-volatile memory cell having a structure having improved integration and simplified electrode wiring structure. The programmable non-volatile memory cell of the present invention adopts a mono-layer gate scheme to simplify the electrode wiring structure and to eliminate a current leakage problem of an insulating film between electrodes. A side and bottom of a semiconductor region, which is disposed directly below a capacity electrode section with a gate insulating film interposed therebetween that compose a control electrode, are isolated from another semiconductor region and semiconductor substrate by insulating films. Thus, a high programming control voltage which is not limited by a junction yield voltage between the semiconductor regions and semiconductor substrate may be applied. Due to that, an area of the capacity electrode section of a floating electrode may be considerably reduced.

摘要翻译： 具有改进的集成和简化的电极布线结构的结构的非易失性存储单元。 本发明的可编程非易失性存储单元采用单层栅极方案来简化电极布线结构，并消除电极之间绝缘膜的漏电问题。 通过绝缘膜将另一个半导体区域的半导体区域和半导体区域的半导体区域和半导体衬底的另一个半导体区域和半导体衬底隔离，其中，半导体区域的一侧和底部直接配置在其间具有构成控制电极的栅极绝缘膜 因此，可以应用不受半导体区域和半导体衬底之间的接合屈服电压限制的高编程控制电压。 因此，浮动电极的电容电极部分的面积可以大大减小。

公开(公告)号：US5592015A

公开(公告)日：1997-01-07

申请号：US547740

申请日：1995-10-26

申请人： Makio Iida ,  Tadashi Shibata ,  Takayuki Sugisaka ,  Shoji Miura ,  Toshio Sakakibara

发明人： Makio Iida ,  Tadashi Shibata ,  Takayuki Sugisaka ,  Shoji Miura ,  Toshio Sakakibara

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/762 ,  H01L21/763 ,  H01L27/02 ,  H01L29/732 ,  H01L29/00 ,  H01L23/58

CPC分类号： H01L29/7322 ,  H01L21/76264 ,  H01L21/763 ,  H01L27/0248 ,  H01L21/76286

摘要： A semiconductor device is provided which makes a high withstand voltage bipolar transistor small and prevents deterioration in a switching speed of the transistor. A silicon oxide layer is formed on a silicon substrate, and a semiconductor island of one conductivity type which is isolated laterally by an isolation trench is formed on the silicon oxide layer. A silicon oxide film is formed on an outer periphery portion of the semiconductor island to bury the trench. In the semiconductor island, a bipolar transistor, namely a base region of the other conductivity type, is formed, and in the base region an emitter region of one conductivity type is formed and a collector region of one conductivity type is further formed. In the semiconductor island a diffusion region of the other conductivity type for extracting excessive carriers to which a constant electric potential is applied is further formed.

摘要翻译： 提供一种半导体器件，其使得高耐压双极晶体管变小，并防止晶体管的开关速度的劣化。 在硅衬底上形成硅氧化物层，在氧化硅层上形成由隔离沟侧向隔离的一种导电型半导体岛。 在半导体岛的外周部形成有氧化硅膜，以埋置沟槽。 在半导体岛中，形成双极晶体管，即另一种导电型的基极区域，在基极区域形成一个导电型的发射极区域，并进一步形成一种导电型的集电极区域。 在半导体岛中，进一步形成用于提取施加恒定电位的过量载流子的另一导电类型的扩散区域。

公开(公告)号：US5557134A

公开(公告)日：1996-09-17

申请号：US341977

申请日：1994-11-16

申请人： Takayuki Sugisaka ,  Toshio Sakakibara ,  Shoji Miura ,  Makio Iida

发明人： Takayuki Sugisaka ,  Toshio Sakakibara ,  Shoji Miura ,  Makio Iida

IPC分类号： H01L21/322 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L29/73 ,  H01L29/732 ,  H01L29/866 ,  H01L29/00

CPC分类号： H01L21/76264 ,  H01L21/3226 ,  H01L21/763 ,  H01L29/7317 ,  H01L29/732 ,  H01L21/76275 ,  H01L21/76286

摘要： A dielectric isolated type semiconductor device which can achieve a reduction in crystalline defects by means of a simple production process is provided. High-concentration regions are formed as active regions on a surface portion of an islandish semiconductor region which is isolated from an adjacent semiconductor region by means of an isolation trench. According to a first aspect of the present invention, an N type crystalline defect suppression region doped at a high concentration and deeper than the high-concentration regions is formed over the entire surface of an adjacent semiconductor region. According to a second aspect of the present invention, a high-concentration N type crystalline defect suppression region is provided on a surface portion of a P type high-concentration region is formed with identical structure and by an identical production process. By means of these N type regions, crystalline defects are reduced.

摘要翻译： 提供了一种能够通过简单的制造工艺实现结晶缺陷降低的绝缘隔离型半导体器件。 在通过隔离沟槽与相邻的半导体区域隔离的岛状半导体区域的表面部分上形成高浓度区域作为有源区域。 根据本发明的第一方面，在相邻的半导体区域的整个表面上形成了在高浓度区域和高浓度区域掺杂的N型晶体缺陷抑制区域。 根据本发明的第二方面，在P型高浓度区域的表面部分上形成高浓度的N型结晶缺陷抑制区域，其结构相同，生产方法相同。 通过这些N型区域，晶体缺陷减少。

公开(公告)号：US5284794A

公开(公告)日：1994-02-08

申请号：US960298

申请日：1992-10-13

申请人： Yoshihiko Isobe ,  Makio Iida ,  Shoji Miura ,  Keizou Kajiura ,  Mikimasa Suzuki ,  Masami Saito

发明人： Yoshihiko Isobe ,  Makio Iida ,  Shoji Miura ,  Keizou Kajiura ,  Mikimasa Suzuki ,  Masami Saito

IPC分类号： H01L21/02 ,  H01L21/26

CPC分类号： H01L28/24 ,  H01L28/40 ,  Y10S148/055 ,  Y10S148/136 ,  Y10S438/94

摘要： A semiconductor device has a thin-film resistor trimmed by laser. The semiconductor device comprises a semiconductor substrate having an element region that covers at least part of the surface of the semiconductor substrate, a first insulation film disposed on the surface of the semiconductor substrate, and a second insulation film disposed on the surface of the semiconductor substrate through an opening of the first insulation film. The opening is formed by selectively removing at least part of the first insulation film at a location on the surface of the semiconductor substrate where the element region is not involved. The thin-film resistor is formed on the second insulation film.

摘要翻译： 半导体器件具有通过激光器修整的薄膜电阻器。 半导体器件包括具有覆盖半导体衬底的表面的至少一部分的元件区域的半导体衬底，设置在半导体衬底的表面上的第一绝缘膜和设置在半导体衬底的表面上的第二绝缘膜 通过第一绝缘膜的开口。 通过在不涉及元件区域的半导体衬底的表面上的位置处选择性地去除第一绝缘膜的至少一部分来形成开口。 薄膜电阻器形成在第二绝缘膜上。