公开(公告)号：US20080185651A1

公开(公告)日：2008-08-07

申请号：US12007318

申请日：2008-01-09

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  H01L27/0266 ,  H01L29/78

Abstract: An SOI type semiconductor device having a silicon substrate and a buried oxide layer formed on the silicon substrate includes an internal circuit formed in a first region having at least one FD type transistor having a SOI structure, the internal circuit performing a function of the semiconductor device and a protection circuit formed in a second region having at least one PD type transistor having a SOI structure, the protection circuit protecting the internal circuit from electro static damage.

Abstract translation: 具有在硅衬底上形成的硅衬底和掩埋氧化层的SOI型半导体器件包括形成在具有SOI结构的至少一个FD型晶体管的第一区域中的内部电路，该内部电路执行半导体器件的功能 以及形成在具有至少一个具有SOI结构的PD型晶体管的第二区域中的保护电路，所述保护电路保护所述内部电路免受静电损坏。

公开(公告)号：US07205190B2

公开(公告)日：2007-04-17

申请号：US10963835

申请日：2004-10-14

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: H01L21/8238

CPC classification number: H01L29/66772 ,  H01L21/84 ,  H01L29/458 ,  H01L29/78612 ,  H01L29/78648 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention adequately activates a substrate contact region of a support substrate without substantially changing the conventional SOI-CMOS device formation process. An exposed face of the support substrate is formed in an element isolation region of a layered substrate, which includes a support substrate having a first semiconductor layer, an insulating layer provided on the support substrate, and a second semiconductor layer provided on the insulating layer, by etching away the insulating layer and the second semiconductor layer. A substrate contact region is then formed in the support substrate by performing ion implantation from the side of the exposed face of the support substrate. Thereafter, an element isolation insulation layer is formed on the exposed face of the support substrate and a gate oxide film and a gate electrode are formed on the remaining second semiconductor layer. In addition, drain and source regions are formed by performing the ion implantation to the remaining second semiconductor layer with the gate electrode serving as a mask. Annealing to activate the substrate contact region, the drain region and the source region is then performed. Thereafter, a metal layer with a high melting point is formed on the drain and source regions and the metal layer is silicided through heat treatment.

Abstract translation: 本发明充分激活支撑衬底的衬底接触区域，而基本上不改变传统的SOI-CMOS器件形成过程。 支撑基板的露出面形成在层叠基板的元件隔离区域中，该层叠基板包括具有第一半导体层的支撑基板，设置在支撑基板上的绝缘层，以及设置在绝缘层上的第二半导体层， 通过蚀刻掉绝缘层和第二半导体层。 然后通过从支撑衬底的暴露面的侧面进行离子注入，在支撑衬底中形成衬底接触区域。 此后，在支撑基板的露出面上形成元件隔离绝缘层，在剩余的第二半导体层上形成栅氧化膜和栅电极。 此外，通过以栅电极作为掩模对剩余的第二半导体层进行离子注入来形成漏极和源极区。 然后进行退火以激活基板接触区域，漏极区域和源极区域。 此后，在漏极和源极区域上形成具有高熔点的金属层，并且通过热处理将金属层硅化。

公开(公告)号：US06849883B2

公开(公告)日：2005-02-01

申请号：US10392930

申请日：2003-03-21

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L29/161 ,  H01L31/072

CPC classification number: H01L21/823412 ,  H01L27/088 ,  H01L29/1054

Abstract: A MOSFET device including a semiconductor substrate, an SiGe layer provided on top of the semiconductor substrate, an Si layer provided on top of the SiGe layer; and a first isolation region for separating the Si layer into a first region and a second region, wherein the Si layer in the second region is turned into an Si epitaxial layer greater in thickness than the Si layer in the first region. The MOSFET device further includes at least one first MOSFET with the Si layer in the first region serving as a strained Si channel, and at least one second MOSFET with the Si epitaxial layer serving as an Si channel.

Abstract translation: 包括半导体衬底的MOSFET器件，设置在半导体衬底顶部的SiGe层，设置在SiGe层顶部的Si层; 以及用于将Si层分离成第一区域和第二区域的第一隔离区域，其中第二区域中的Si层变成比第一区域中的Si层厚度更大的Si外延层。 MOSFET器件还包括至少一个第一MOSFET，其中第一区域中的Si层用作应变Si沟道，以及至少一个第二MOSFET，其中Si外延层用作Si沟道。

公开(公告)号：US06075270A

公开(公告)日：2000-06-13

申请号：US126844

申请日：1998-07-31

Applicant: Masao Okihara ,  Hidetsugu Uchida

Inventor： Masao Okihara ,  Hidetsugu Uchida

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/78 ,  H01L29/04

CPC classification number: H01L29/66477 ,  H01L21/2815 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/7834 ,  H01L21/28114 ,  H01L21/28123

Abstract: A field effect transistor and a method for forming the field effect transistor are made up of a source region which is formed on the substrate, a drain region which is formed on the substrate, a stepped portion which is formed in the substrate between the source region and the drain region, a gate insulating film which is formed on the stepped portion of the substrate, and a gate electrode which is formed on the gate insulating film, wherein, a thickness of the gate insulating film near the drain region, which is less than that of the gate insulating film on a channel region defined in the substrate between the source region and the drain region. Accordingly, the field effect transistor and a method for forming the field effect transistor can prevent degradation of transistor characteristics because of a hot carrier effect.

Abstract translation: 场效应晶体管和形成场效应晶体管的方法由形成在基板上的源极区域，形成在基板上的漏极区域，形成在源极区域之间的基板中的台阶部分 漏极区域，形成在基板的阶梯部上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极，其中，漏极区域附近的栅极绝缘膜的厚度较小 比在源极区域和漏极区域之间的衬底中限定的沟道区域上的栅极绝缘膜的栅极绝缘膜的厚度大。 因此，场效应晶体管和形成场效应晶体管的方法可以防止由于热载流子效应导致的晶体管特性的劣化。

公开(公告)号：US08071415B2

公开(公告)日：2011-12-06

申请号：US12659601

申请日：2010-03-15

Applicant: Tomohiro Okamura ,  Masao Okihara

Inventor： Tomohiro Okamura ,  Masao Okihara

IPC: H01L21/00

CPC classification number: H01L27/14 ,  H01L27/144

Abstract: There is provided a method of fabricating a semiconductor device having plural light receiving elements, and having an amplifying element, the method including: a) forming an active region on the semiconductor substrate for configuring the amplifying element; b) forming a light receiving element region on the semiconductor substrate for forming the plural light receiving elements, with the active region acting as a reference for positioning; c) implanting an impurity into the light receiving element region; d) repeating the process b) and the process c) a number of times that equals a number of diffusion layers in the light receiving element region; e) after implanting the impurity, performing a drive-in process to carry out drive in of the semiconductor substrate; and f) the process e), forming an amplifying element forming process by implanting an impurity in the active region.

Abstract translation: 提供一种制造具有多个光接收元件并具有放大元件的半导体器件的方法，该方法包括：a）在半导体衬底上形成用于配置放大元件的有源区; b）在所述半导体衬底上形成用于形成所述多个光接收元件的受光元件区域，所述有源区域用作定位的基准; c）将杂质注入光接收元件区域; d）重复步骤b）和过程c）等于光接收元件区域中的多个扩散层的次数; e）在注入杂质之后，执行驱动工艺以进行半导体衬底的驱动; 和f）工艺e），通过在有源区中注入杂质形成放大元件形成工艺。

公开(公告)号：US07985638B2

公开(公告)日：2011-07-26

申请号：US12487952

申请日：2009-06-19

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: H01L21/336

CPC classification number: H01L29/42384 ,  H01L21/28052 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/6653

Abstract: A semiconductor device manufacturing method which sequentially forms a gate oxide film and gate electrode material over a semiconductor layer of an SOI substrate and patterns the material into gate electrodes. The method further comprises the steps of forming sidewalls made of an insulator to cover side surfaces of the gate electrode; ion-implanting into the semiconductor layer on both sides of the gate electrode to form drain/source regions; partially etching the sidewalls to expose upper parts of the side surfaces of the gate electrode; depositing a metal film to cover the tops of the drain/source regions and of the gate electrode and the exposed upper parts of the side surfaces of the gate electrode; and performing heat treatment on the SOI substrate to form silicide layers respectively in the surfaces of the gate electrode and of the drain/source regions.

Abstract translation: 一种在SOI衬底的半导体层上依次形成栅极氧化膜和栅电极的半导体器件制造方法，并将该材料图案化成栅电极。 该方法还包括以下步骤：形成由绝缘体制成的侧壁以覆盖栅电极的侧表面; 离子注入到栅极两侧的半导体层中以形成漏极/源极区; 部分蚀刻侧壁以暴露栅电极的侧表面的上部; 沉积金属膜以覆盖漏极/源极区域以及栅电极的顶部和栅电极的侧表面的暴露的上部; 对SOI衬底进行热处理，分别在栅极电极和漏极/源极区域的表面形成硅化物层。

公开(公告)号：US20100248410A1

公开(公告)日：2010-09-30

申请号：US12659601

申请日：2010-03-15

Applicant: Tomohiro Okamura ,  Masao Okihara

Inventor： Tomohiro Okamura ,  Masao Okihara

IPC: H01L31/18

CPC classification number: H01L27/14 ,  H01L27/144

Abstract: There is provided a method of fabricating a semiconductor device having plural light receiving elements, and having an amplifying element, the method including: a) forming an active region on the semiconductor substrate for configuring the amplifying element; b) forming a light receiving element region on the semiconductor substrate for forming the plural light receiving elements, with the active region acting as a reference for positioning; c) implanting an impurity into the light receiving element region; d) repeating the process b) and the process c) a number of times that equals a number of diffusion layers in the light receiving element region; e) after implanting the impurity, performing a drive-in process to carry out drive in of the semiconductor substrate; and f) the process e), forming an amplifying element forming process by implanting an impurity in the active region.

Abstract translation: 提供一种制造具有多个光接收元件并具有放大元件的半导体器件的方法，该方法包括：a）在半导体衬底上形成用于配置放大元件的有源区; b）在所述半导体衬底上形成用于形成所述多个光接收元件的受光元件区域，所述有源区域用作定位的基准; c）将杂质注入光接收元件区域; d）重复步骤b）和过程c）等于光接收元件区域中的多个扩散层的次数; e）在注入杂质之后，执行驱动工艺以进行半导体衬底的驱动; 和f）工艺e），通过在有源区中注入杂质形成放大元件形成工艺。

公开(公告)号：US20100244135A1

公开(公告)日：2010-09-30

申请号：US12659947

申请日：2010-03-25

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  H01L21/823814 ,  H01L21/823878

Abstract: In a semiconductor device of a silicon on insulator (SOI) structure having uniform transistor properties, a first distance between a gate electrode forming position of an N type transistor and an end of a P type semiconductor region is greater than a second distance between a gate electrode forming position of the P type transistor and an edge of the N type semiconductor region.

Abstract translation: 在具有均匀晶体管特性的绝缘体上硅（SOI）结构的半导体器件中，N型晶体管的栅电极形成位置与P型半导体区域的端部之间的第一距离大于栅极之间的第二距离 P型晶体管的电极形成位置和N型半导体区域的边缘。

公开(公告)号：US20080233664A1

公开(公告)日：2008-09-25

申请号：US12073493

申请日：2008-03-06

Applicant: Michihiro Ebe ,  Masao Okihara

Inventor： Michihiro Ebe ,  Masao Okihara

IPC: H01L21/66 ,  C23F1/08

CPC classification number: H01L22/20 ,  H01L21/2007 ,  H01L22/12

Abstract: A semiconductor integrated circuit production method prepares an SOI layer thickness database that correlates measurement data of each SOI layer thickness with each SOI substrate identification data. The production method extracts the measurement data for each SOI substrate from the SOI layer thickness database, and carries out layer thickness adjustment surface treatment for the SOI substrates based on these data. A semiconductor integrated circuit production device includes an SOI layer thickness database storage unit for storing the SOI layer thickness database, and a layer thickness adjustment conditions control unit for extracting the measurement data for each SOI substrate from the SOI layer thickness database and deciding conditions for the layer thickness adjustment surface treatment based on these data. The semiconductor integrated circuit production device also includes a surface treatment unit that adjusts SOI layer thickness by carrying out the surface treatment on the SOI layers in accordance with the decided conditions.

Abstract translation: 半导体集成电路制造方法制备将每个SOI层厚度的测量数据与每个SOI衬底识别数据相关联的SOI层厚度数据库。 该制造方法从SOI层厚度数据库中提取每个SOI衬底的测量数据，并且基于这些数据对SOI衬底进行层厚调整表面处理。 半导体集成电路制造装置包括用于存储SOI层厚度数据库的SOI层厚度数据库存储单元和用于从SOI层厚度数据库提取每个SOI衬底的测量数据的层厚调整条件控制单元， 基于这些数据的层厚调整表面处理。 半导体集成电路制造装置还包括：表面处理单元，其通过根据所确定的条件对SOI层进行表面处理来调整SOI层的厚度。

公开(公告)号：US20050176184A1

公开(公告)日：2005-08-11

申请号：US10963835

申请日：2004-10-14

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: H01L21/762 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/522 ,  H01L27/08 ,  H01L27/092 ,  H01L29/45 ,  H01L29/786 ,  H01L21/00 ,  H01L21/8234 ,  H01L29/74

CPC classification number: H01L29/66772 ,  H01L21/84 ,  H01L29/458 ,  H01L29/78612 ,  H01L29/78648 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention adequately activates a substrate contact region of a support substrate without substantially changing the conventional SOI-CMOS device formation process. An exposed face of the support substrate is formed in an element isolation region of a layered substrate, which includes a support substrate having a first semiconductor layer, an insulating layer provided on the support substrate, and a second semiconductor layer provided on the insulating layer, by etching away the insulating layer and the second semiconductor layer. A substrate contact region is then formed in the support substrate by performing ion implantation from the side of the exposed face of the support substrate. Thereafter, an element isolation insulation layer is formed on the exposed face of the support substrate and a gate oxide film and a gate electrode are formed on the remaining second semiconductor layer. In addition, drain and source regions are formed by performing the ion implantation to the remaining second semiconductor layer with the gate electrode serving as a mask. Annealing to activate the substrate contact region, the drain region and the source region is then performed. Thereafter, a metal layer with a high melting point is formed on the drain and source regions and the metal layer is silicided through heat treatment.

Abstract translation: 本发明充分激活支撑衬底的衬底接触区域，而基本上不改变传统的SOI-CMOS器件形成过程。 支撑基板的露出面形成在分层基板的元件隔离区域中，该层叠基板的元件隔离区域包括具有第一半导体层的支撑基板，设置在支撑基板上的绝缘层，以及设置在绝缘层上的第二半导体层， 通过蚀刻掉绝缘层和第二半导体层。 然后通过从支撑衬底的暴露面的侧面进行离子注入，在支撑衬底中形成衬底接触区域。 此后，在支撑基板的露出面上形成元件隔离绝缘层，在剩余的第二半导体层上形成栅氧化膜和栅电极。 此外，通过以栅电极作为掩模对剩余的第二半导体层进行离子注入来形成漏极和源极区。 然后进行退火以激活基板接触区域，漏极区域和源极区域。 此后，在漏极和源极区域上形成具有高熔点的金属层，并且通过热处理将金属层硅化。