公开(公告)号：US06075270A

公开(公告)日：2000-06-13

申请号：US126844

申请日：1998-07-31

Applicant: Masao Okihara ,  Hidetsugu Uchida

Inventor： Masao Okihara ,  Hidetsugu Uchida

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/78 ,  H01L29/04

CPC classification number: H01L29/66477 ,  H01L21/2815 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/7834 ,  H01L21/28114 ,  H01L21/28123

Abstract: A field effect transistor and a method for forming the field effect transistor are made up of a source region which is formed on the substrate, a drain region which is formed on the substrate, a stepped portion which is formed in the substrate between the source region and the drain region, a gate insulating film which is formed on the stepped portion of the substrate, and a gate electrode which is formed on the gate insulating film, wherein, a thickness of the gate insulating film near the drain region, which is less than that of the gate insulating film on a channel region defined in the substrate between the source region and the drain region. Accordingly, the field effect transistor and a method for forming the field effect transistor can prevent degradation of transistor characteristics because of a hot carrier effect.

Abstract translation: 场效应晶体管和形成场效应晶体管的方法由形成在基板上的源极区域，形成在基板上的漏极区域，形成在源极区域之间的基板中的台阶部分 漏极区域，形成在基板的阶梯部上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极，其中，漏极区域附近的栅极绝缘膜的厚度较小 比在源极区域和漏极区域之间的衬底中限定的沟道区域上的栅极绝缘膜的栅极绝缘膜的厚度大。 因此，场效应晶体管和形成场效应晶体管的方法可以防止由于热载流子效应导致的晶体管特性的劣化。

公开(公告)号：US20060079031A1

公开(公告)日：2006-04-13

申请号：US11155610

申请日：2005-06-20

Applicant: Hidetsugu Uchida

Inventor： Hidetsugu Uchida

IPC: H01L21/84

CPC classification number: H01L21/86 ,  H01L29/6678 ,  H01L29/78657

Abstract: An insulating film layer is formed between a channel region of an MOS element formed in a monocrystal silicon layer of an SOS substrate in which the monocrystal silicon layer is laminated on a sapphire substrate, and the sapphire substrate, thereby to bring a stress state of the monocrystal silicon layer on the insulating film layer into a tensile stress state.

Abstract translation: 在形成在单晶硅层的蓝宝石衬底上的SOS衬底的单晶硅层中形成的MOS元件的沟道区域和蓝宝石衬底之间形成绝缘膜层，从而使得 绝缘膜层上的单晶硅层变成拉伸应力状态。

公开(公告)号：US06524968B2

公开(公告)日：2003-02-25

申请号：US09970692

申请日：2001-10-05

Applicant: Masashi Takahashi ,  Toshio Nagata ,  Yoshirou Tsurugida ,  Takashi Ohsako ,  Hirotaka Mori ,  Akihiko Ohara ,  Hidetsugu Uchida ,  Hiroaki Uchida ,  Katsuji Yoshida ,  Masahiro Takahashi

Inventor： Masashi Takahashi ,  Toshio Nagata ,  Yoshirou Tsurugida ,  Takashi Ohsako ,  Hirotaka Mori ,  Akihiko Ohara ,  Hidetsugu Uchida ,  Hiroaki Uchida ,  Katsuji Yoshida ,  Masahiro Takahashi

IPC: H01L2131

CPC classification number: H01L21/28211 ,  H01L21/02238 ,  H01L21/02337 ,  H01L21/02359 ,  H01L21/31662

Abstract: A method for forming an insulating film is provided which is capable of inhibiting spontaneous growth of a silicon oxide film formed on a silicon substrate and an increase in thickness of a film caused by exposure to an atmosphere. After having allowed a silicon dioxide layer with a predetermined thickness to grow on a surface of a silicon crystal, a surface of the silicon dioxide is exposed to organic gas containing no hydroxyl group or is exposed to ammonia gas.

Abstract translation: 提供一种形成绝缘膜的方法，其能够抑制在硅衬底上形成的氧化硅膜的自发生长和由暴露于大气中引起的膜的厚度增加。 在允许具有预定厚度的二氧化硅层在硅晶体的表面上生长之后，二氧化硅的表面暴露于不含羟基的有机气体或暴露于氨气中。

公开(公告)号：US07879657B2

公开(公告)日：2011-02-01

申请号：US11155610

申请日：2005-06-20

Applicant: Hidetsugu Uchida

Inventor： Hidetsugu Uchida

IPC: H01L21/00 ,  H01L21/335

CPC classification number: H01L21/86 ,  H01L29/6678 ,  H01L29/78657

Abstract: An insulating film layer is formed between a channel region of an MOS element formed in a monocrystal silicon layer of an SOS substrate in which the monocrystal silicon layer is laminated on a sapphire substrate, and the sapphire substrate, thereby to bring a stress state of the monocrystal silicon layer on the insulating film layer into a tensile stress state.

Abstract translation: 在形成在单晶硅层的蓝宝石衬底上的SOS衬底的单晶硅层中形成的MOS元件的沟道区域和蓝宝石衬底之间形成绝缘膜层，从而使得 绝缘膜层上的单晶硅层变成拉伸应力状态。

公开(公告)号：US6037588A

公开(公告)日：2000-03-14

申请号：US20505

申请日：1998-02-09

Applicant: Guo-Lin Liu ,  Hidetsugu Uchida ,  Izumi Aikawa ,  Naokatsu Ikegami ,  Norio Hirashita

Inventor： Guo-Lin Liu ,  Hidetsugu Uchida ,  Izumi Aikawa ,  Naokatsu Ikegami ,  Norio Hirashita

IPC: G01N23/225 ,  G01N27/62 ,  H01L21/66 ,  H01J37/29

CPC classification number: G01N23/2258 ,  H01J2237/2527

Abstract: In order to achieve a method for analyzing the compositional distribution of deposited film adhering to the internal surface of a contact hole having a diameter in the deep submicron order, primary ions 18 are radiated into the surface 12a of an insulating film 12 where the contact hole 14 is formed to generate secondary ions 20. The primary ions are radiated into the surface of the insulating film from a constant diagonal direction. Then, mass spectrometry is performed on the resulting secondary ions to detect the compositional distribution of the deposited film 16 formed at the internal surface of the contact hole. Thus, the compositional distribution of the deposited film is ascertained over the depth-wise direction of the contact hole.

Abstract translation: 为了实现分析附着在深亚微米级直径的接触孔的内表面的沉积膜的组成分布的方法，将一次离子18照射到绝缘膜12的表面12a中，其中接触孔 14形成以产生二次离子20.初级离子从恒定的对角线方向辐射到绝缘膜的表面中。 然后，对得到的二次离子进行质谱分析，以检测形成在接触孔的内表面的沉积膜16的组成分布。 因此，在接触孔的深度方向上确定沉积膜的组成分布。

公开(公告)号：US4920391A

公开(公告)日：1990-04-24

申请号：US332584

申请日：1989-04-03

Applicant: Hidetsugu Uchida

Inventor： Hidetsugu Uchida

IPC: G11C11/402 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/7827 ,  H01L27/108 ,  H01L29/78642

Abstract: In a semiconductor memory device formed on a semiconductor substrate (11), a first FET (21) is formed on a substrate. A first polysilicon film (13) serves as a gate electrode of this first FET (21). A second polysilicon film (16) is formed over the first polysilicon film (13), being separated by an insulating film (15). A third polysilicon film (20) is formed on the top and sides of the second polysilicon film (16). The third polysilicon film (20) has an impurity-doped region (19). A lower end (20a) of the third polysilicon film (20) is in contact with the first polysilicon film (13). The first, second and third polysilicon films (13, 16, 20) form a second FET (22), with the second polysilicon film (16) forming a gate electrode, and that part of the third polysilicon film (20) which is between the impurity-doped region (19) and the contacting end (20a) and adjacent to the second polysilicon film (16 ) forming a channel.

Abstract translation: 在形成在半导体衬底（11）上的半导体存储器件中，在衬底上形成第一FET（21）。 第一多晶硅膜（13）用作该第一FET（21）的栅电极。 第一多晶硅膜（13）上形成第二多晶硅膜（16），被绝缘膜（15）隔开。 在第二多晶硅膜（16）的顶部和侧面上形成第三多晶硅膜（20）。 第三多晶硅膜（20）具有杂质掺杂区域（19）。 第三多晶硅膜（20）的下端（20a）与第一多晶硅膜（13）接触。 第一，第二和第三多晶硅膜（13,16,20）形成第二FET（22），第二多晶硅膜（16）形成栅电极，第三多晶硅膜（20）的部分位于 杂质掺杂区域（19）和接触端（20a）并与第二多晶硅膜（16）相邻，形成通道。

公开(公告)号：US4907197A

公开(公告)日：1990-03-06

申请号：US218303

申请日：1988-07-12

Applicant: Hidetsugu Uchida

Inventor： Hidetsugu Uchida

IPC: H01L27/112 ,  G11C16/04 ,  H01L21/8246 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/7883 ,  G11C16/0425

Abstract: A non-volatile semiconductor memory device includes a semiconductor substrate, and a source and a drain of a MOS transistor formed on one surface of the semiconductor substrate and spaced about from each other. First, second and third gates are formed on one side of the substrate through an insulating film and between the source and the drain of the MOS transistor. This memory device has one transistor construction and can be fabricated simply and finely.

Abstract translation: 非易失性半导体存储器件包括半导体衬底，以及形成在半导体衬底的一个表面上且彼此间隔开的MOS晶体管的源极和漏极。 首先，第二和第三栅极通过绝缘膜并且在MOS晶体管的源极和漏极之间形成在衬底的一侧上。 该存储器件具有一个晶体管结构，并且可以简单且精细地制造。

公开(公告)号：US20090090919A1

公开(公告)日：2009-04-09

申请号：US12230774

申请日：2008-09-04

Applicant: Hidetsugu Uchida

Inventor： Hidetsugu Uchida

IPC: H01L21/28 ,  H01L29/24

CPC classification number: H01L29/7802 ,  H01L21/049 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66068

Abstract: A semiconductor device includes a silicon carbide substrate having a channel region formed on a surface thereof; a silicon layer formed on the channel region; a gate insulation film formed on the silicon layer; and a gate electrode formed on the gate insulation film. A method of producing a semiconductor device includes the steps of: forming a silicon layer on a surface of a silicon carbide substrate; forming a gate insulation film on the silicon layer to form a laminated structure of the silicon layer and the gate insulation film; and forming a gate electrode on the gate insulation film.

Abstract translation: 半导体器件包括在其表面上形成有沟道区的碳化硅衬底; 形成在沟道区上的硅层; 形成在硅层上的栅极绝缘膜; 以及形成在栅极绝缘膜上的栅电极。 一种制造半导体器件的方法包括以下步骤：在碳化硅衬底的表面上形成硅层; 在硅层上形成栅极绝缘膜，形成硅层和栅极绝缘膜的叠层结构; 以及在栅极绝缘膜上形成栅电极。

公开(公告)号：US06229175B1

公开(公告)日：2001-05-08

申请号：US09272313

申请日：1999-03-19

Applicant: Hidetsugu Uchida

Inventor： Hidetsugu Uchida

IPC: H01L29788

CPC classification number: H01L21/28273 ,  H01L29/42324 ,  H01L29/511

Abstract: A nonvolatile memory includes a charge transfer layer, having a low barrier height, between the floating gate electrode and the control gate electrode. Accordingly, the nonvolatile memory avoids the problem in which the number of program and erasure cycles is decreased as a result of degradation of a tunnel oxide film.

Abstract translation: 非易失性存储器包括在浮置栅极电极和控制栅电极之间具有低势垒高度的电荷转移层。 因此，非易失性存储器避免了作为隧道氧化物膜劣化的结果，编程和擦除循环的数量减少的问题。