公开(公告)号：US08261034B1

公开(公告)日：2012-09-04

申请号：US12638205

申请日：2009-12-15

申请人： Weining Li

发明人： Weining Li

IPC分类号： G06F12/00

CPC分类号： G06T1/20 ,  G06T1/60

摘要： A method for moving data in a memory system of a cascading region-based filter is disclosed. The method generally includes steps (A) to (C). Step (A) may load a first portion of the data from a buffer to the memory system at a start of a given cycle using a control circuit. The memory system generally has multiple first memories. A first region of a particular first memory may receive the first portion of data. Step (B) may copy the data in a second region of the particular first memory to a third region of the particular first memory at an end of the given cycle. Step (C) may copy the data in an output region of the particular first memory to an input region of a next first memory at the end of the given cycle. The output region generally overlaps both the first region and the second region.

摘要翻译： 公开了一种用于在基于级联区域的滤波器的存储器系统中移动数据的方法。 该方法通常包括步骤（A）至（C）。 步骤（A）可以使用控制电路在给定周期的开始时将数据的第一部分从缓冲器加载到存储器系统。 存储器系统通常具有多个第一存储器。 特定第一存储器的第一区域可以接收第一部分数据。 在给定周期结束时，步骤（B）可将特定第一存储器的第二区域中的数据复制到特定第一存储器的第三区域。 步骤（C）可以在给定周期结束时将特定第一存储器的输出区域中的数据复制到下一个第一存储器的输入区域。 输出区域通常与第一区域和第二区域重叠。

公开(公告)号：US06521540B1

公开(公告)日：2003-02-18

申请号：US09345357

申请日：1999-07-01

申请人： Weining Li

发明人： Weining Li

IPC分类号： H01L21302

CPC分类号： H01L21/76897 ,  H01L21/76829 ,  H01L21/76832

摘要： An improved and new process for fabricating self-aligned contacts (SAC) to source/drain areas of complimentary (CMOS) FET's has been developed using a non-conformal layer of silicon nitride, eliminating the need for a hard mask. This process allows for “zero” spacing from contact structure to polysilicon gate structure, for closely spaced design rule gates. Some key process features of this invention are as follows: no hard mask is needed and the gate process is exactly the same as “standard” logic process. The process differences are that between the S/D implant, salicidation and the normal contact process, there is inserted a non-conformal CVD silicon nitride deposition with a SAC pattern and etch process. The process is fully compatible with both state of-the-art salicide and polycide processes. The self-aligned contact process simplifies processing, while yielding improvements in electrical device performance and reliability. The process is very useful for the “standard” logic device salicided processes.

摘要翻译： 已经开发了使用非保形层氮化硅制造自对准接触（SAC）到互补（CMOS）FET的源极/漏极区域的改进和新工艺，从而消除了对硬掩模的需要。 该过程允许从接触结构到多晶硅栅极结构的“零”间隔，用于紧密间隔的设计规则栅极。 本发明的一些关键过程特征如下：不需要硬掩模，并且门过程与“标准”逻辑过程完全相同。 工艺差异在于在S / D植入物，盐化和正常接触过程之间，插入具有SAC图案和蚀刻工艺的非保形CVD氮化硅沉积。 该过程完全兼容最先进的杀虫剂和多杀菌剂过程。 自对准接触过程简化了处理，同时提高了电气设备的性能和可靠性。 该过程对于“标准”逻辑器件浸水过程非常有用。

公开(公告)号：US06509264B1

公开(公告)日：2003-01-21

申请号：US09537480

申请日：2000-03-30

申请人： Weining Li ,  Yung Tao Lin

发明人： Weining Li ,  Yung Tao Lin

IPC分类号： H01L2144

CPC分类号： H01L29/6653 ,  H01L21/28518 ,  H01L29/665

摘要： A new method of forming MOS transistors with self-aligned silicide has been achieved. A gate oxide layer is formed overlying a semiconductor substrate. A polysilicon layer is deposited. The polysilicon layer and the gate oxide layer are patterned to form gates. Ions are implanted to form lightly doped drain regions. A dielectric layer is deposited. The dielectric layer is polished down to expose the top surface of the gates. The dielectric layer is then anisotropically etched down to form dielectric sidewall spacers. The dielectric sidewall spacers cover a portion of the vertical sidewalls of the gates while exposing a portion of the vertical sidewalls of the gates. Ions are implanted to form source and drain regions. A metal layer is deposited. Contact surfaces are formed between the metal layer with: the exposed top surfaces of the gates, the exposed portions of the vertical sidewalls of the gates, and the exposed source and drain regions. The integrated circuit device is annealed to react the metal layer and the polysilicon layer and silicon to selectively form a silicide layer in the surface of the polysilicon layer and in the surface of the semiconductor substrate at the contact surfaces. The remaining metal layer is removed to complete the device.

摘要翻译： 已经实现了用自对准硅化物形成MOS晶体管的新方法。 在半导体衬底上形成栅氧化层。 沉积多晶硅层。 图案化多晶硅层和栅极氧化层以形成栅极。 植入离子以形成轻掺杂的漏极区。 沉积介电层。 将电介质层抛光以露出栅极的顶表面。 然后将介电层各向异性地向下蚀刻以形成电介质侧壁间隔物。 电介质侧壁间隔物在露出栅极的垂直侧壁的一部分的同时覆盖栅极的垂直侧壁的一部分。 植入离子以形成源区和漏区。 沉积金属层。 在金属层之间形成接触表面，其中：暴露的栅极顶表面，栅极的垂直侧壁的暴露部分以及暴露的源极和漏极区域。 对集成电路器件进行退火以使金属层和多晶硅层和硅反应以在多晶硅层的表面和接触表面的半导体衬底的表面中选择性地形成硅化物层。 去除剩余的金属层以完成该装置。

公开(公告)号：US6093602A

公开(公告)日：2000-07-25

申请号：US356007

申请日：1999-07-16

申请人： Weining Li ,  Lin Yung Tao ,  Ramachandramurthy Pradeep Yelehanka ,  Tin Tin Wee

发明人： Weining Li ,  Lin Yung Tao ,  Ramachandramurthy Pradeep Yelehanka ,  Tin Tin Wee

IPC分类号： H01L21/768 ,  H01L21/8244 ,  H01L27/11 ,  H01L21/8242

CPC分类号： H01L27/11 ,  H01L21/76895 ,  H01L27/1104

摘要： A method of fabricating local interconnects of polycide has been achieved. A substrate is provided. Narrowly spaced features, such as MOS transistor gates and polysilicon traces, are provided overlying the substrate. A dielectric layer is deposited overlying the substrate and the narrowly spaced features. The dielectric layer is patterned to form openings between the narrowly spaced features for planned contacts to the surface of the substrate. A doped polysilicon layer is deposited overlying the dielectric layer and filling the openings. The doped polysilicon layer is etched down to the top surface of the narrowly spaced features. The doped polysilicon layer remains in the spaces between the narrowly spaced features. A polycide layer is formed overlying the narrowly spaced features and the doped polysilicon layer. The polycide layer and the doped polysilicon layer are patterned to complete the contacts and create the local interconnects of polycide, and the integrated circuit device is completed.

摘要翻译： 已经实现了制造多孔体的局部互连的方法。 提供基板。 在衬底上提供窄间隔的特征，例如MOS晶体管栅极和多晶硅迹线。 沉积在衬底上的电介质层和狭窄间隔的特征。 对电介质层进行图案化以在狭缝间隔的特征之间形成开口，用于与衬底表面的规划接触。 沉积覆盖介质层并填充开口的掺杂多晶硅层。 掺杂的多晶硅层被蚀刻到窄间隔的特征的顶表面。 掺杂多晶硅层保留在狭窄间隔的特征之间的空间中。 覆盖窄间隔的特征和掺杂多晶硅层形成多晶硅化物层。 将多晶硅层和掺杂多晶硅层图案化以完成触点并产生多晶硅化物的局部互连，并且完成集成电路器件。

公开(公告)号：US06649461B1

公开(公告)日：2003-11-18

申请号：US10132356

申请日：2002-04-25

申请人： Tommy Mau Lam Lai ,  Weining Li ,  Yung Tao Lin

发明人： Tommy Mau Lam Lai ,  Weining Li ,  Yung Tao Lin

IPC分类号： H01L218238

CPC分类号： H01L21/76224 ,  H01L21/823814 ,  H01L21/823878

摘要： A new angle implant is provided that reduces or eliminates the effects of narrow channel impurity diffusion to surrounding regions of insulation. The invention provides for angle implantation of p-type impurities into corners of STI regions that are adjacent to NMOS devices and angle implantation of n-type impurities into corners of STI regions that are adjacent to PMOS devices.

摘要翻译： 提供了一种新的角度注入，其减少或消除了窄通道杂质扩散对周围绝缘区域的影响。 本发明提供了将p型杂质角度注入到与NMOS器件相邻的STI区域的角部，并且将n型杂质角度注入到与PMOS器件相邻的STI区域的拐角中。

公开(公告)号：US06177304B1

公开(公告)日：2001-01-23

申请号：US09298933

申请日：1999-04-26

申请人： Weining Li ,  Yung-Tao Lin ,  Mau Lam Lai ,  Tin Tin Wee

发明人： Weining Li ,  Yung-Tao Lin ,  Mau Lam Lai ,  Tin Tin Wee

IPC分类号： H01L218238

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/823475 ,  H01L21/823481

摘要： A method for integrating salicide and self-aligned contact processes in the fabrication of logic circuits with embedded memory is described. Isolation areas are formed on a semiconductor substrate surrounding and electrically isolating device areas. Gate electrodes and associated source and drain regions are formed on and in the semiconductor substrate wherein the gate electrodes have silicon nitride sidewall spacers. A metal silicide layer is formed on the top surface of the gate electrodes and on the top surface of the semiconductor substrate overlying the source and drain regions associated with the gate electrodes using a salicide process. A poly-cap layer is deposited overlying the substrate. The poly-cap layer is selectively removed overlying one of the salicided source and drain regions where a self-aligned contact is to be formed, and overlying another of the salicided source and drain regions and a portion of its associated salicided gate electrode where a butted contact is to be formed. An insulating layer is deposited over the surface of the semiconductor substrate. The insulating layer is etched through to form simultaneously the planned self-aligned contact opening and the planned butted contact opening. The self-aligned contact opening and the butted contact opening are filled with a conducting layer to complete fabrication of the integrated circuit device.

摘要翻译： 描述了在具有嵌入式存储器的逻辑电路的制造中整合自杀化和自对准接触过程的方法。 隔离区域形成在围绕并电隔离器件区域的半导体衬底上。 栅极电极和相关的源极和漏极区域形成在半导体衬底上和栅极中具有氮化硅侧壁间隔物。 使用自对准硅化物工艺在栅电极的顶表面和半导体衬底的顶表面上形成金属硅化物层，覆盖与栅电极相关的源极和漏极区域。 多层覆盖层沉积在衬底上。 选择性地去除聚盖层，覆盖其中要形成自对准接触的水银源区和漏区之一，并且覆盖另一个水银源和漏区及其相关联的盐化栅极的一部分，其中对接 接触将被形成。 绝缘层沉积在半导体衬底的表面上。 绝缘层被蚀刻通过以形成计划的自对准接触开口和计划的对接接触开口。 自对准的接触开口和对接的接触开口填充有导电层，以完成集成电路器件的制造。

公开(公告)号：US08817132B1

公开(公告)日：2014-08-26

申请号：US12690302

申请日：2010-01-20

申请人： Weining Li

发明人： Weining Li

IPC分类号： H04N9/64

CPC分类号： H04N5/367 ,  H04N5/3765

摘要： A method for synchronizing a first circuit to an electro-optical sensor is disclosed. The method generally includes steps (A) to (D). Step (A) may generate with the first circuit a configuration signal that conveys a request to capture at least one frame of a plurality of periodic frames. Step (B) may receive the periodic frames at a second circuit from the electro-optical sensor. Step (C) may discard a first frame of the periodic frames where the first frame precedes the request. Step (D) may store a plurality of active pixels in a second frame of the periodic frames in a memory where the second frame follows the request. The second circuit is generally a hardware implementation.

摘要翻译： 公开了一种使第一电路与电光传感器同步的方法。 该方法通常包括步骤（A）至（D）。 步骤（A）可以利用第一电​​路产生传送请求以捕获多个周期性帧的至少一个帧的配置信号。 步骤（B）可以在来自电光传感器的第二电路处接收周期性帧。 步骤（C）可以丢弃其中第一帧在请求之前的周期性帧的第一帧。 步骤（D）可将多个有源像素存储在周期性帧的第二帧中，其中第二帧遵循该请求。 第二电路通常是硬件实现。

公开(公告)号：US06376298B1

公开(公告)日：2002-04-23

申请号：US09494636

申请日：2000-01-31

申请人： Weining Li ,  Yung-Tao Lin

发明人： Weining Li ,  Yung-Tao Lin

IPC分类号： H01L218234

CPC分类号： H01L21/76897 ,  H01L21/823481

摘要： A method for integrating salicide and self-aligned contact processes in the fabrication of integrated circuits by using a poly cap mask and a special layout technique is described. A pair of gate electrodes and associated source and drain regions are formed overlying a semiconductor substrate wherein nitride spacers are formed on sidewalls of the gate electrodes. A poly-cap layer is deposited overlying the gate electrodes and source and drain regions. The poly-cap layer is selectively removed overlying one of the source and drain regions between the gate electrode pair where a self-aligned contact is to be formed and removed over one of the gate electrode pair. An insulating layer is deposited over the surface of the semiconductor substrate. The planned self-aligned contact opening is made through the insulating layer to the source/drain region to be contacted wherein the contact opening partially overlies the poly-cap layer over the adjacent gate electrode of the pair. The self-aligned contact opening is filled with a conducting layer to complete fabrication of the integrated circuit device.

摘要翻译： 描述了通过使用聚盖掩模和特殊布局技术在集成电路的制造中整合自对准和自对准接触工艺的方法。 一对栅电极和相关的源极和漏极区域形成在半导体衬底上，其中在栅电极的侧壁上形成氮化物间隔物。 覆盖栅电极和源极和漏极区的多晶硅层被沉积。 选择性地去除聚盖层，覆盖栅极电极对之间的源极和漏极区域之一，其中将形成自对准接触并在栅极电极对中的一个上去除。 绝缘层沉积在半导体衬底的表面上。 计划的自对准接触开口通过绝缘层到待接触的源极/漏极区域，其中接触开口部分地覆盖在该对的相邻栅电极上的多晶硅层。 自对准接触开口填充有导电层以完成集成电路器件的制造。