公开(公告)号：US11737285B2

公开(公告)日：2023-08-22

申请号：US17202296

申请日：2021-03-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kai Hsu ,  Hui-Lin Wang ,  Kun-I Chou ,  Ching-Hua Hsu ,  Ju-Chun Fan ,  Yi-Yu Lin ,  Hung-Yueh Chen

IPC: H10B61/00 ,  H10N50/80

CPC classification number: H10B61/22 ,  H10N50/80

Abstract: A memory array includes at least one strap region having therein a plurality of source line straps and a plurality of word line straps, and at least two sub-arrays having a plurality of staggered, active magnetic storage elements. The at least two sub-arrays are separated by the strap region. A plurality of staggered, dummy magnetic storage elements is disposed within the strap region.

公开(公告)号：US20230240151A1

公开(公告)日：2023-07-27

申请号：US18122730

申请日：2023-03-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Si-Han Tsai ,  Che-Wei Chang ,  Po-Kai Hsu ,  Jing-Yin Jhang ,  Yu- Ping Wang ,  Ju-Chun Fan ,  Ching-Hua Hsu ,  Yi-Yu Lin ,  Hung-Yueh Chen

IPC: H10B61/00 ,  H10N50/20 ,  H10N50/80 ,  H10N50/01

CPC classification number: H10B61/00 ,  H10N50/01 ,  H10N50/20 ,  H10N50/80

Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.

公开(公告)号：US20220393103A1

公开(公告)日：2022-12-08

申请号：US17363023

申请日：2021-06-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Si-Han Tsai ,  Ching-Hua Hsu ,  Chen-Yi Weng ,  Po-Kai Hsu ,  Jing-Yin Jhang

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22

Abstract: A method for fabricating a magnetic random access memory (MRAM) device includes the steps of first forming a first magnetic tunneling junction (MTJ) on a substrate, forming a first top electrode on the first MTJ, and then forming a passivation layer around the first MTJ. Preferably, the passivation layer includes a V-shape and a valley point of the V-shape is higher than a top surface of the first top electrode.

公开(公告)号：US20220271088A1

公开(公告)日：2022-08-25

申请号：US17202296

申请日：2021-03-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kai Hsu ,  Hui-Lin Wang ,  Kun-I Chou ,  Ching-Hua Hsu ,  Ju-Chun Fan ,  Yi-Yu Lin ,  Hung-Yueh Chen

IPC: H01L27/22 ,  H01L43/02

Abstract: A memory array includes at least one strap region having therein a plurality of source line straps and a plurality of word line straps, and at least two sub-arrays having a plurality of staggered, active magnetic storage elements. The at least two sub-arrays are separated by the strap region. A plurality of staggered, dummy magnetic storage elements is disposed within the strap region.

公开(公告)号：US20220115587A1

公开(公告)日：2022-04-14

申请号：US17090859

申请日：2020-11-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Ju-Chun Fan ,  Yi-Yu Lin ,  Ching-Hua Hsu ,  Hung-Yueh Chen

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10

Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.

公开(公告)号：US20220059618A1

公开(公告)日：2022-02-24

申请号：US17033901

申请日：2020-09-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kai Hsu ,  Hui-Lin Wang ,  Ching-Hua Hsu ,  Yi-Yu Lin ,  Ju-Chun Fan ,  Hung-Yueh Chen

IPC: H01L27/24 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  H01L45/00

Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.

公开(公告)号：US12232425B2

公开(公告)日：2025-02-18

申请号：US18515273

申请日：2023-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Si-Han Tsai ,  Dong-Ming Wu ,  Chen-Yi Weng ,  Ching-Hua Hsu ,  Ju-Chun Fan ,  Yi-Yu Lin ,  Che-Wei Chang ,  Po-Kai Hsu ,  Jing-Yin Jhang

IPC: G11C11/00 ,  G11C11/16 ,  H01F10/32 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.

公开(公告)号：US11957061B2

公开(公告)日：2024-04-09

申请号：US18200592

申请日：2023-05-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Ju-Chun Fan ,  Yi-Yu Lin ,  Ching-Hua Hsu ,  Hung-Yueh Chen

IPC: H10N50/10 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/10 ,  H10B61/22 ,  H10N50/80 ,  H10N50/85

Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts top surfaces of the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.

公开(公告)号：US11917923B2

公开(公告)日：2024-02-27

申请号：US17242322

申请日：2021-04-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Ching-Hua Hsu ,  Si-Han Tsai ,  Shun-Yu Huang ,  Chen-Yi Weng ,  Ju-Chun Fan ,  Che-Wei Chang ,  Yi-Yu Lin ,  Po-Kai Hsu ,  Jing-Yin Jhang ,  Ya-Jyuan Hung

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H01L27/22 ,  H01L43/12

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10

Abstract: A magnetoresistive random access memory (MRAM) structure, including a substrate and multiple MRAM cells on the substrate, wherein the MRAM cells are arranged in a memory region adjacent to a logic region. An ultra low-k (ULK) layer covers the MRAM cells, wherein the surface portion of ultra low-k layer is doped with fluorine, and dents are formed on the surface of ultra low-k layer at the boundaries between the memory region and the logic region.

公开(公告)号：US20240065108A1

公开(公告)日：2024-02-22

申请号：US17944242

申请日：2022-09-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Ching-Hua Hsu ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Po-Kai Hsu

IPC: H01L43/12 ,  H01L43/08 ,  G11C11/16 ,  H01L43/02 ,  H01L27/22 ,  H01L43/10

CPC classification number: H01L43/12 ,  H01L43/08 ,  G11C11/161 ,  H01L43/02 ,  H01L27/222 ,  H01L43/10

Abstract: The high-density MRAM device of the present invention has a second interlayer dielectric (ILD) layer covering the capping layer in the MRAM cell array area and the logic area. The thickness of the second ILD layer in the MRAM cell array area is greater than that in the logic area. The composition of the second ILD layer in the logic area is different from the composition of the second ILD layer in the MRAM cell array area.