公开(公告)号：US09443927B2

公开(公告)日：2016-09-13

申请号：US14446344

申请日：2014-07-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lu-An Chen ,  Tien-Hao Tang

IPC: H01L23/62 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/0619 ,  H01L29/0692 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/7816

Abstract: A semiconductor device includes a substrate, a gate positioned on the substrate, a drain region and a source region formed in the substrate at two respectively sides of the gate, a first well region formed in the substrate, and a plurality of first doped islands formed in the source region. The drain region and the source region include a first conductivity, and the first well region and the first doped islands include a second conductivity. The source region is formed in the first well region, and the first doped islands are spaced apart from the first well region.

Abstract translation: 半导体器件包括衬底，位于衬底上的栅极，在栅极的两个侧面处形成在衬底中的源极区和形成在衬底中的源极区，形成在衬底中的第一阱区，以及形成的多个第一掺杂岛 在源区。 漏区和源极区包括第一导电性，第一阱区和第一掺杂岛包括第二导电性。 源极区形成在第一阱区中，并且第一掺杂岛与第一阱区间隔开。

公开(公告)号：US09343567B2

公开(公告)日：2016-05-17

申请号：US14454739

申请日：2014-08-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ning He ,  Jhih-Ming Wang ,  Lu-An Chen ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L27/02 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L27/0248 ,  H01L27/0262 ,  H01L27/027 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1083

Abstract: A semiconductor device is includes a substrate, a gate positioned on the substrate, and a drain region and a source region formed at two respective sides of the gate in the substrate. The drain region includes a first doped region having a first conductivity type, a second doped region having a second conductivity type, and a third doped region. The first conductivity type and the second conductivity type are complementary to each other. The semiconductor device further includes a first well region formed under the first doped region, a second well region formed under the second doped region, and a third well region formed under the third doped region. The first well region, the second well region, and the third well region all include the first conductivity type. A concentration of the second well region is different from a concentration of the third well region.

Abstract translation: 半导体器件包括衬底，位于衬底上的栅极和形成在衬底中的栅极的两个相应侧的漏极区域和源极区域。 漏区包括具有第一导电类型的第一掺杂区，具有第二导电类型的第二掺杂区和第三掺杂区。 第一导电类型和第二导电类型彼此互补。 半导体器件还包括形成在第一掺杂区下的第一阱区，形成在第二掺杂区下的第二阱区，以及形成在第三掺杂区下的第三阱区。 第一阱区域，第二阱区域和第三阱区域都包括第一导电类型。 第二阱区域的浓度不同于第三阱区域的浓度。

公开(公告)号：US09142545B2

公开(公告)日：2015-09-22

申请号：US14181740

申请日：2014-02-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Chun Chen ,  Li-Cih Wang ,  Lu-An Chen ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L27/06

CPC classification number: H01L27/0262 ,  H01L27/0259 ,  H01L27/0921

Abstract: The electrostatic discharge protection structure includes an N-well disposed on a substrate, a P-well disposed on the substrate and adjacent to the N-well, a first doped region of N-type conductivity disposed in the N-well, a second doped region of N-type conductivity disposed in the N-well, a third doped region of P-type conductivity disposed in the N-well, a fifth doped region of P-type conductivity disposed in the P-well, a fourth doped region of N-type conductivity disposed between the third doped region and the fifth doped region in the P-well, an anode electrically connected to the first doped region and the second doped region, and a cathode electrically connected to the fourth doped region and the fifth doped region.

Abstract translation: 静电放电保护结构包括设置在衬底上的N阱，设置在衬底上并与N阱相邻的P阱，设置在N阱中的N型导电性的第一掺杂区，第二掺杂 设置在N阱中的N型导电性区域，设置在N阱中的P型导电体的第三掺杂区域，设置在P阱中的P型导电性的第五掺杂区域，第四掺杂区域 设置在P阱中的第三掺杂区域和第五掺杂区域之间的N型导电体，与第一掺杂区域和第二掺杂区域电连接的阳极，以及电连接到第四掺杂区域和第五掺杂区域的阴极 地区。

公开(公告)号：US09142540B2

公开(公告)日：2015-09-22

申请号：US13873261

申请日：2013-04-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Ning He ,  Lu-An Chen ,  Tien-Hao Tang

IPC: H01L23/552 ,  H01L27/02

CPC classification number: H01L27/0248 ,  H01L27/0266 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7816

Abstract: A semiconductor device includes a substrate, a gate positioned on the substrate, a drain and a source formed in the substrate at respective two sides of the gate, and a doped region formed in the source. The drain and the source comprise a first conductivity type and the doped region comprises a second conductivity type. The first conductivity type and the second conductivity type are complementary to each other.

Abstract translation: 半导体器件包括衬底，位于衬底上的栅极，在栅极的相应两侧在衬底中形成的漏极和源极以及形成在源极中的掺杂区域。 漏极和源极包括第一导电类型，并且掺杂区域包括第二导电类型。 第一导电类型和第二导电类型彼此互补。

公开(公告)号：US20150243776A1

公开(公告)日：2015-08-27

申请号：US14188645

申请日：2014-02-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lu-An Chen ,  Tien-Hao Tang

IPC: H01L29/78 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/7835

Abstract: A laterally diffused metal oxide semiconductor (LDMOS) is provided. A substrate has a deep well with a second conductive type therein. A gate is disposed on the substrate. A first doped region of a second conductive type and a second doped region of a first conductive type are located in the deep well and at the corresponding two sides of the gate. A drain region of a second conductive type is located in the first doped region. A drain contact is disposed on the drain region. A doped region of a first conductive type is located in the first doped region and under the drain region but not directly below the drain contact. A source region is located in the second doped region. A field drift metal oxide semiconductor (FDMOS) which is similar to the laterally diffused metal oxide semiconductor (LDMOS) is also provided.

Abstract translation: 提供了横向扩散的金属氧化物半导体（LDMOS）。 衬底具有深阱，其中具有第二导电类型。 栅极设置在基板上。 第一导电类型的第一掺杂区域和第一导电类型的第二掺杂区域位于深阱中并且位于栅极的相应两侧。 第二导电类型的漏极区位于第一掺杂区域中。 漏极接触件设置在漏极区域上。 第一导电类型的掺杂区域位于第一掺杂区域中且位于漏极区域下方，但不位于漏极触点下方。 源极区域位于第二掺杂区域中。 还提供了类似于横向扩散的金属氧化物半导体（LDMOS）的场漂移金属氧化物半导体（FDMOS）。

公开(公告)号：US20150236010A1

公开(公告)日：2015-08-20

申请号：US14181740

申请日：2014-02-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Chun Chen ,  Li-Cih Wang ,  Lu-An Chen ,  Tien-Hao Tang

IPC: H01L27/02 ,  H01L27/06

CPC classification number: H01L27/0262 ,  H01L27/0259 ,  H01L27/0921

Abstract: The electrostatic discharge protection structure includes an N-well disposed on a substrate, a P-well disposed on the substrate and adjacent to the N-well, a first doped region of N-type conductivity disposed in the N-well, a second doped region of N-type conductivity disposed in the N-well, a third doped region of P-type conductivity disposed in the N-well, a fifth doped region of P-type conductivity disposed in the P-well, a fourth doped region of N-type conductivity disposed between the third doped region and the fifth doped region in the P-well, an anode electrically connected to the first doped region and the second doped region, and a cathode electrically connected to the fourth doped region and the fifth doped region.

Abstract translation: 静电放电保护结构包括设置在衬底上的N阱，设置在衬底上并与N阱相邻的P阱，设置在N阱中的N型导电性的第一掺杂区，第二掺杂 设置在N阱中的N型导电性区域，设置在N阱中的P型导电体的第三掺杂区域，设置在P阱中的P型导电性的第五掺杂区域，第四掺杂区域 设置在P阱中的第三掺杂区域和第五掺杂区域之间的N型导电体，与第一掺杂区域和第二掺杂区域电连接的阳极，以及电连接到第四掺杂区域和第五掺杂区域的阴极 地区。