公开(公告)号：US10283614B1

公开(公告)日：2019-05-07

申请号：US15886724

申请日：2018-02-01

Applicant: United Microelectronics Corp.

Inventor： Ming-Chang Lu ,  Wei Chen

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/20 ,  H01L29/267 ,  H01L21/02 ,  H01L29/43 ,  H01L29/778 ,  H01L29/417

Abstract: Provided is a semiconductor structure including a substrate, a first semiconductor layer, a second semiconductor layer, a gate electrode, a source electrode and a drain electrode. The first semiconductor layer contains a group III-V-VI semiconductor compound layer and is disposed on the substrate. The second semiconductor layer includes a group III-V semiconductor compound and is disposed on the first semiconductor layer. The gate electrode is disposed on the second semiconductor layer. The source electrode and the drain electrode are disposed on the second semiconductor layer beside the gate electrode.

公开(公告)号：US20190074357A1

公开(公告)日：2019-03-07

申请号：US15696167

申请日：2017-09-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Chih Lai ,  Ming-Chang Lu ,  Wei Chen ,  Hui-Lin Wang ,  Yi-Ting Liao ,  Chin-Fu Lin

IPC: H01L29/10 ,  H01L29/24 ,  H01L29/51 ,  H01L21/385 ,  H01L29/66

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a first gradient layer, two source/drain structures, a second gradient layer, and a gate. The first gradient layer is disposed on the substrate. The two source/drain structures are separately disposed on the first gradient layer. The second gradient layer is disposed on the two source/drain structures and the first gradient layer, and a second portion of the second gradient layer directly contacts a first portion of the first gradient layer. The gate is disposed on the second gradient layer, between the two source/drain structures.

公开(公告)号：US20250017117A1

公开(公告)日：2025-01-09

申请号：US18236923

申请日：2023-08-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuan-Hsiang Chen ,  Yi-Ching Wang ,  Wei Chen ,  Chia-Fu Cheng ,  Chun-Yao Yang

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/20 ,  H10N50/85

Abstract: A magnetic memory device includes a magnetic tunneling junction (MTJ) stack and a capping layer on the MTJ stack. The MTJ stack includes a reference layer, a tunneling barrier layer on the reference layer, and a free layer on the tunneling barrier layer. The capping layer includes a metal under layer that is in direct contact with the free layer, an oxide capping layer on the metal under layer, and a metal protection layer on the oxide capping layer.

公开(公告)号：US11545521B2

公开(公告)日：2023-01-03

申请号：US17157952

申请日：2021-01-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei Chen ,  Hui-Lin Wang ,  Yu-Ru Yang ,  Chin-Fu Lin ,  Yi-Syun Chou ,  Chun-Yao Yang

IPC: H01L27/22 ,  H01L23/552 ,  H01L43/10 ,  H01F41/34 ,  H01L43/02 ,  G11C11/16 ,  H01F10/32 ,  H01L43/12

Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a magnetic shielding layer. The two magnetic tunnel junction elements are arranged side by side. The magnetic shielding layer is disposed between the magnetic tunnel junction elements. A method of forming said magnetic tunnel junction (MTJ) device includes the following steps. An interlayer including a magnetic shielding layer is formed. The interlayer is etched to form recesses in the interlayer. The magnetic tunnel junction elements fill in the recesses. Or, a method of forming said magnetic tunnel junction (MTJ) device includes the following steps. A magnetic tunnel junction layer is formed. The magnetic tunnel junction layer is patterned to form magnetic tunnel junction elements. An interlayer including a magnetic shielding layer is formed between the magnetic tunnel junction elements.

公开(公告)号：US20210343935A1

公开(公告)日：2021-11-04

申请号：US16884060

申请日：2020-05-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Wei Chen ,  Po-Kai Hsu ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H01L43/12 ,  H01L43/02 ,  H01F10/32

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection and a second metal interconnection in the first IMD layer; forming a channel layer on the first metal interconnection and the second metal interconnection; forming a magnetic tunneling junction (MTJ) stack on the channel layer; and removing the MTJ stack to form a MTJ.