公开(公告)号：US20150214114A1

公开(公告)日：2015-07-30

申请号：US14166091

申请日：2014-01-28

Applicant: United Microelectronics Corp.

Inventor： Po-Cheng Huang ,  Yu-Ting Li ,  Wu-Sian Sie ,  Yi-Liang Liu ,  Chun-Hsiung Wang ,  Kun-Ju Li ,  Chia-Lin Hsu ,  Chih-Chien Liu

IPC: H01L21/8234 ,  H01L29/423 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/66 ,  H01L21/321

CPC classification number: H01L21/823437 ,  H01L21/31051 ,  H01L21/31055 ,  H01L29/66545

Abstract: A manufacturing method of a semiconductor structure is disclosed. The manufacturing method includes the following steps. A substrate with a plurality of dummy gate structures formed thereon and a first dielectric layer covering the dummy gate structures is provided, the dummy gate structures comprising a plurality of dummy gates and a plurality of insulating layers formed on the dummy gates, wherein at least two of the dummy gate structures have different heights. A first planarization process is performed to expose at least one of the dummy gate structures having the highest height. A first etching process is performed to expose the insulating layers. A chemical mechanical polishing (CMP) process with a non-selectivity slurry is performed to planarize the dummy gate structures. The planarized dummy gate structures are removed to form a plurality of gate trenches.

Abstract translation: 公开了一种半导体结构的制造方法。 该制造方法包括以下步骤。 提供具有形成在其上的多个虚拟栅极结构的基板和覆盖该虚拟栅极结构的第一介电层，所述伪栅极结构包括形成在所述伪栅极上的多个伪栅极和多个绝缘层，其中至少两个 的虚拟门结构具有不同的高度。 执行第一平面化处理以暴露具有最高高度的虚拟栅极结构中的至少一个。 执行第一蚀刻工艺以暴露绝缘层。 进行具有非选择性浆料的化学机械抛光（CMP）工艺以使虚拟栅极结构平坦化。 平面化的虚拟栅极结构被去除以形成多个栅极沟槽。