公开(公告)号：US10276367B1

公开(公告)日：2019-04-30

申请号：US15865263

申请日：2018-01-09

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Jen-Chieh Lin ,  Wen-Chin Lin ,  Yu-Ting Li

IPC: H01L21/02 ,  H01L21/302 ,  H01L21/321 ,  H01L21/768 ,  H01L21/306

Abstract: A method for improving wafer surface uniformity is disclosed. A wafer including a first region and a second region is provided. The first region and the second region have different pattern densities. A conductive layer is formed on the wafer. A buffer layer is then formed on the conductive layer. The buffer layer is polished until the conductive layer is exposed. A portion of the conductive layer and the remaining buffer layer are etched away.

公开(公告)号：US20180197749A1

公开(公告)日：2018-07-12

申请号：US15862564

申请日：2018-01-04

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Po-Cheng Huang ,  Yu-Ting Li ,  Fu-Shou Tsai ,  Wen-Chin Lin ,  Chun-Liang Liu

IPC: H01L21/321 ,  H01L27/108 ,  H01L21/306 ,  H01L21/762 ,  H01L21/3105

Abstract: A planarization method is provided and includes the following steps. A substrate having a main surface is provided. A protruding structure is formed on the main surface. An insulating layer is formed conformally covering the main surface and the top surface and the sidewall of the protruding structure. A stop layer is formed on the insulating layer and at least covers the top surface of the protruding structure. A first dielectric layer is formed blanketly covering the substrate and the protruding structure and a chemical mechanical polishing process is then performed to remove a portion of the first dielectric layer until a portion of the stop layer is exposed thereby obtaining an upper surface. A second dielectric layer having a pre-determined thickness is formed covering the upper surface.

公开(公告)号：US09905430B1

公开(公告)日：2018-02-27

申请号：US15245194

申请日：2016-08-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Shou Tsai ,  Yu-Ting Li ,  Li-Chieh Hsu ,  Yi-Liang Liu ,  Kun-Ju Li ,  Po-Cheng Huang ,  Chien-Nan Lin

IPC: H01L21/84 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/311 ,  H01L21/8234

CPC classification number: H01L21/31055 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02227 ,  H01L21/02271 ,  H01L21/31111 ,  H01L21/823431

Abstract: A method for forming a semiconductor structure includes following steps. A substrate is provided, and a semiconductor layer is formed on the substrate. Next, a SiN-rich pre-oxide layer is formed on the semiconductor layer. After forming the SiN-rich pre-oxide layer, an anneal treatment is performed to partially transfer the SiN-rich pre-oxide layer to form a SiN layer and a SiO layer. And the SiO layer is formed the on the SiN layer. Subsequently, a planarization process is performed to remove a portion of the SiO layer to expose the SiN layer.

公开(公告)号：US20180033633A1

公开(公告)日：2018-02-01

申请号：US15220365

申请日：2016-07-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Fu-Shou Tsai ,  Yu-Ting Li ,  Li-Chieh Hsu ,  Yi-Liang Liu ,  Kun-Ju Li ,  Po-Cheng Huang ,  Chien-Nan Lin

IPC: H01L21/308 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/027

CPC classification number: H01L21/3081 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0273 ,  H01L21/302 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/31056 ,  H01L21/31058 ,  H01L21/3212

Abstract: A method for planarizing a silicon layer includes providing a silicon layer having at least one recess therein. Next, a photoresist layer is formed to cover the silicon layer and fill up the recess. Then, the photoresist layer is hardened. After that, part of the photoresist layer is removed by taking a top surface of the silicon layer as a stop layer. Finally the photoresist layer and the silicon layer are etched back simultaneously to remove the photoresist layer entirely.

公开(公告)号：US20160351674A1

公开(公告)日：2016-12-01

申请号：US15232796

申请日：2016-08-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Po-Cheng Huang ,  Yu-Ting Li ,  Jen-Chieh Lin ,  Chih-Hsun Lin ,  Tzu-Hsiang Hung ,  Wu-Sian Sie ,  I-Lun Hung ,  Wen-Chin Lin ,  Chun-Tsen Lu

IPC: H01L29/423 ,  H01L21/66 ,  H01L29/51 ,  H01L21/324 ,  H01L29/66 ,  H01L21/02 ,  H01L21/321

CPC classification number: H01L29/42364 ,  H01L21/02271 ,  H01L21/02354 ,  H01L21/02362 ,  H01L21/31051 ,  H01L21/3212 ,  H01L21/324 ,  H01L21/823437 ,  H01L22/12 ,  H01L22/20 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A semiconductor process includes the following steps. A dielectric layer is formed on a substrate, where the dielectric layer has at least a dishing from a first top surface. A shrinkable layer is formed to cover the dielectric layer, where the shrinkable layer has a second top surface. A treatment process is performed to shrink a part of the shrinkable layer according to a topography of the second top surface, thereby flattening the second top surface. A semiconductor structure formed by said semiconductor process is also provided.

Abstract translation: 半导体工艺包括以下步骤。 电介质层形成在基板上，其中电介质层至少具有来自第一顶表面的凹陷。 形成可收缩层以覆盖电介质层，其中可收缩层具有第二顶表面。 执行处理过程以根据第二顶表面的形貌收缩可收缩层的一部分，从而使第二顶表面变平。 还提供了由所述半导体工艺形成的半导体结构。

公开(公告)号：US09502303B2

公开(公告)日：2016-11-22

申请号：US14682265

申请日：2015-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Kuo-Chin Hung ,  Po-Cheng Huang ,  Yu-Ting Li ,  Wu-Sian Sie ,  Chun-Tsen Lu ,  Wen-Chin Lin ,  Fu-Shou Tsai

IPC: H01L21/768 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/285

CPC classification number: H01L21/823475 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/32133 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823871

Abstract: A method for manufacturing a semiconductor device is provided. A substrate with an insulation formed thereon is provided, wherein the insulation has plural trenches, and the adjacent trenches are spaced apart from each other. A barrier layer is formed on an upper surface of the insulation and in sidewalls of the trenches, and the barrier layer comprises overhung portions corresponding to the trenches. A seed layer is formed on the barrier layer. Then, an upper portion of the seed layer formed on an upper surface of the barrier layer is removed. An upper portion of the barrier layer is removed for exposing the upper surface of the insulation. Afterwards, the conductors are deposited along the seed layer for filling up the trenches, wherein the top surfaces of the conductors are substantially aligned with the upper surface of the insulation.

Abstract translation: 提供一种制造半导体器件的方法。 提供其上形成有绝缘体的基板，其中绝缘体具有多个沟槽，并且相邻的沟槽彼此间隔开。 在绝缘体的上表面和沟槽的侧壁中形成阻挡层，并且阻挡层包括对应于沟槽的悬垂部分。 种子层形成在阻挡层上。 然后，除去形成在阻挡层的上表面上的种子层的上部。 去除阻挡层的上部以暴露绝缘体的上表面。 之后，导体沿种子层沉积以填充沟槽，其中导体的顶表面基本上与绝缘体的上表面对齐。

公开(公告)号：US20160300765A1

公开(公告)日：2016-10-13

申请号：US14682265

申请日：2015-04-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kun-Ju Li ,  Kuo-Chin Hung ,  Po-Cheng Huang ,  Yu-Ting Li ,  Wu-Sian Sie ,  Chun-Tsen Lu ,  Wen-Chin Lin ,  Fu-Shou Tsai

IPC: H01L21/8234 ,  H01L21/3213 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L21/823475 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/32133 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823871

Abstract: A method for manufacturing a semiconductor device is provided. A substrate with an insulation formed thereon is provided, wherein the insulation has plural trenches, and the adjacent trenches are spaced apart from each other. A barrier layer is formed on an upper surface of the insulation and in sidewalls of the trenches, and the barrier layer comprises overhung portions corresponding to the trenches. A seed layer is formed on the barrier layer. Then, an upper portion of the seed layer formed on an upper surface of the barrier layer is removed. An upper portion of the barrier layer is removed for exposing the upper surface of the insulation. Afterwards, the conductors are deposited along the seed layer for filling up the trenches, wherein the top surfaces of the conductors are substantially aligned with the upper surface of the insulation.

Abstract translation: 提供一种制造半导体器件的方法。 提供其上形成有绝缘体的基板，其中绝缘体具有多个沟槽，并且相邻的沟槽彼此间隔开。 在绝缘体的上表面和沟槽的侧壁中形成阻挡层，并且阻挡层包括对应于沟槽的悬垂部分。 种子层形成在阻挡层上。 然后，除去形成在阻挡层的上表面上的种子层的上部。 去除阻挡层的上部以暴露绝缘体的上表面。 之后，导体沿种子层沉积以填充沟槽，其中导体的顶表面基本上与绝缘体的上表面对齐。

公开(公告)号：US20150162419A1

公开(公告)日：2015-06-11

申请号：US14102515

申请日：2013-12-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ting Li ,  Po-Cheng Huang ,  Wu-Sian Sie ,  Chun-Hsiung Wang ,  Yi-Liang Liu ,  Chia-Lin Hsu ,  Rai-Min Huang

IPC: H01L29/66 ,  H01L21/321 ,  H01L21/02 ,  H01L21/3205

CPC classification number: H01L29/66545 ,  H01L21/02074 ,  H01L21/02112 ,  H01L21/02318 ,  H01L21/32055 ,  H01L21/3212 ,  H01L29/66795

Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate including at least a fin structure is provided, and a material layer is formed to cover the fin structure. Then, a first planarization process is performed on the material layer to form a first material layer, and an oxide layer is formed on the first material layer. Subsequently, the oxide layer is totally removed to expose the first material layer, and a second material layer is formed in-situ on the first material layer after totally removing the oxide layer.

Abstract translation: 制造半导体器件的方法包括以下步骤。 提供至少包括翅片结构的基板，并且形成材料层以覆盖翅片结构。 然后，在材料层上进行第一平面化处理以形成第一材料层，并且在第一材料层上形成氧化物层。 随后，完全除去氧化物层以露出第一材料层，并且在完全除去氧化物层之后，在第一材料层上原位形成第二材料层。

公开(公告)号：US20140094017A1

公开(公告)日：2014-04-03

申请号：US13633104

申请日：2012-10-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wu-Sian Sie ,  Chun-Wei Hsu ,  Chia-Lung Chang ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Yu-Ting Li ,  Wei-Che Tsao ,  Yen-Ming Chen ,  Chun-Hsiung Wang ,  Chia-Lin Hsu

IPC: H01L21/762

CPC classification number: H01L21/76232 ,  H01L21/76229

Abstract: A manufacturing method for a shallow trench isolation. First, a substrate is provided, a hard mask layer and a patterned photoresist layer are sequentially formed on the substrate, at least one trench is then formed in the substrate through an etching process, the hard mask layer is removed. Afterwards, a filler is formed at least in the trench and a planarization process is then performed on the filler. Since the planarization process is performed only on the filler, so the dishing phenomenon can effectively be avoided.

Abstract translation: 浅沟槽隔离的制造方法。 首先，提供基板，在基板上依次形成硬掩模层和图案化光致抗蚀剂层，然后通过蚀刻工艺在基板中形成至少一个沟槽，去除硬掩模层。 然后，至少在沟槽中形成填料，然后对填料进行平面化处理。 由于仅在填料上进行平坦化处理，所以可以有效地避免凹陷现象。

公开(公告)号：US10923481B2

公开(公告)日：2021-02-16

申请号：US16151323

申请日：2018-10-03

Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

Inventor： Yu-Ting Li ,  Jen-Chieh Lin ,  Wen-Chin Lin ,  Po-Cheng Huang ,  Fu-Shou Tsai

IPC: H01L27/10 ,  H01L27/108 ,  H01L27/06 ,  H01L21/8234

Abstract: A semiconductor IC structure includes a substrate including at least a memory cell region and a peripheral region defined thereon, a plurality of memory cells formed in the memory cell region, at least an active device formed in the peripheral region, a plurality of contact plugs formed in the memory cell region, and at least a bit line formed in the memory cell region. The contact plugs are physically and electrically connected to the bit line. More important, bottom surfaces of the contact plugs are lower a surface of the substrate.