公开(公告)号：US10468417B2

公开(公告)日：2019-11-05

申请号：US15959291

申请日：2018-04-23

申请人： UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Chih-Chien Liu ,  Tzu-Chin Wu ,  Po-Chun Chen ,  Chia-Lung Chang

IPC分类号： H01L23/48 ,  H01L27/108 ,  H01L21/02 ,  H01L21/8234

摘要： A fabricating method of a stop layer includes providing a substrate. The substrate is divided into a memory region and a peripheral circuit region. Two conductive lines are disposed within the peripheral circuit region. Then, an atomic layer deposition is performed to form a silicon nitride layer to cover the conductive lines. Later, after forming the silicon nitride layer, a silicon carbon nitride layer is formed to cover the silicon nitride layer. The silicon carbon nitride layer serves as a stop layer.

公开(公告)号：US10276389B1

公开(公告)日：2019-04-30

申请号：US15987887

申请日：2018-05-23

申请人： UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

发明人： Chih-Chieh Tsai ,  Yi-Wei Chen ,  Pin-Hong Chen ,  Chih-Chien Liu ,  Tzu-Chieh Chen ,  Chun-Chieh Chiu ,  Tsun-Min Cheng ,  Kai-Jiun Chang ,  Chia-Chen Wu ,  Yi-An Huang

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L29/78 ,  H01L29/76 ,  H01L21/28 ,  H01L21/768 ,  H01L29/49 ,  H01L27/108

摘要： A method for fabricating semiconductor device includes the steps of: forming a silicon layer on a substrate; forming a first metal silicon nitride layer on the silicon layer; performing an oxygen treatment process to form an oxide layer on the first metal silicon nitride layer; forming a second metal silicon nitride layer on the oxide layer; forming a conductive layer on the second metal silicon nitride layer; and patterning the conductive layer, the second metal silicon nitride layer, the oxide layer, the first metal silicon nitride layer, and the silicon layer to form a gate structure.

公开(公告)号：US20190115394A1

公开(公告)日：2019-04-18

申请号：US15807528

申请日：2017-11-08

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chih-Chien Liu ,  Chao-Ching Hsieh ,  Yu-Ru Yang ,  Hsiao-Pang Chou

IPC分类号： H01L27/24 ,  H01L45/00 ,  H01L21/02 ,  H01L21/265 ,  H01L29/08

摘要： The present invention provides a semiconductor structure, the semiconductor structure includes a substrate comprising a diffusion region, a transistor structure on the substrate, and a resistive random access memory (RRAM) on the substrate, wherein the resistive random access memory includes at least one metal silicide layer in direct contact with the diffusion region, and a lower electrode, a resistive switching layer and an upper electrode are sequentially disposed on the metal silicide layer.

公开(公告)号：US10177311B1

公开(公告)日：2019-01-08

申请号：US15782836

申请日：2017-10-12

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chao-Ching Hsieh ,  Chih-Chien Liu ,  Yu-Ru Yang ,  Hsiao-Pang Chou

IPC分类号： G11C13/00 ,  H01L45/00 ,  H01L27/24

摘要： A resistive random access memory (RRAM) cell includes a substrate, a transistor having a gate on the substrate and a source/drain region in the substrate, a first inter-layer dielectric layer covering the transistor, a contact plug disposed in the first inter-layer dielectric layer and landing on the source/drain region, a resistive material layer conformally covering a protruding upper end portion of the contact plug, and a top electrode on the resistive material layer.

公开(公告)号：US10141193B2

公开(公告)日：2018-11-27

申请号：US14949896

申请日：2015-11-24

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chin-Cheng Chien ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Teng-Chun Tsai

IPC分类号： H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

摘要： A semiconductor device including a substrate, a spacer and a high-k dielectric layer having a U-shape profile is provided. The spacer located on the substrate surrounds and defines a trench. The high-k dielectric layer having a U-shape profile is located in the trench, and the high-k dielectric layer having a U-shape profile exposes an upper portion of the sidewalls of the trench.

公开(公告)号：US10014227B2

公开(公告)日：2018-07-03

申请号：US14825165

申请日：2015-08-12

申请人： UNITED MICROELECTRONICS CORP.

发明人： Teng-Chun Tsai ,  Chun-Yuan Wu ,  Chih-Chien Liu ,  Chin-Cheng Chien ,  Chin-Fu Lin

IPC分类号： H01L27/092 ,  H01L21/84 ,  H01L29/165 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/10

CPC分类号： H01L21/845 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/165

摘要： A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.

公开(公告)号：US09461150B2

公开(公告)日：2016-10-04

申请号：US14979594

申请日：2015-12-28

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chin-Cheng Chien ,  Hsin-Kuo Hsu ,  Chih-Chien Liu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06 ,  H01L21/311 ,  H01L29/36

CPC分类号： H01L29/66795 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/31111 ,  H01L29/06 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/36 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7853

摘要： A method for fabricating semiconductor device with fin-shaped structure is disclosed. The method includes the steps of: forming a fin-shaped structure on a substrate; forming a first dielectric layer on the substrate and the fin-shaped structure; depositing a second dielectric layer on the first dielectric layer; etching back a portion of the second dielectric layer; removing part of the first dielectric layer to expose a top surface and part of the sidewall of the fin-shaped structure; forming an epitaxial layer to cover the exposed top surface and part of the sidewall of the fin-shaped structure; and removing a portion of the second dielectric layer.

摘要翻译： 公开了一种制造具有鳍状结构的半导体器件的方法。 该方法包括以下步骤：在衬底上形成鳍状结构; 在所述基板上形成第一电介质层和所述鳍状结构; 在所述第一电介质层上沉积第二电介质层; 蚀刻第二介电层的一部分; 去除所述第一电介质层的一部分以暴露所述鳍状结构的顶表面和所述侧壁的一部分; 形成外延层以覆盖所述鳍状结构的暴露的顶表面和所述侧壁的一部分; 以及去除所述第二电介质层的一部分。

公开(公告)号：US20150087126A1

公开(公告)日：2015-03-26

申请号：US14557469

申请日：2014-12-02

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chih-Chien Liu ,  Tzu-Chin Wu ,  Yu-Shu Lin ,  Jei-Ming Chen ,  Wen-Yi Teng

IPC分类号： H01L21/8234 ,  H01L21/02 ,  H01L21/324 ,  H01L29/78

CPC分类号： H01L29/7843 ,  H01L21/02164 ,  H01L21/324 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6653

摘要： A method of fabrication a transistor device with a non-uniform stress layer including the following processes. First, a semiconductor substrate having a first transistor region is provided. A low temperature deposition process is carried out to form a first tensile stress layer on a transistor within the first transistor region, wherein a temperature of the low temperature deposition process is lower than 300 degree Celsius (° C.) . Then, a high temperature annealing process is performed, wherein a temperature of the high temperature annealing process is at least 150° C. higher than a temperature of the low temperature deposition process. Finally, a second tensile stress layer is formed on the first tensile stress layer, wherein the first tensile stress layer has a tensile stress lower than a tensile stress of the second tensile stress layer.

摘要翻译： 一种制造具有不均匀应力层的晶体管器件的方法，包括以下过程。 首先，提供具有第一晶体管区域的半导体衬底。 进行低温沉积工艺以在第一晶体管区域内的晶体管上形成第一拉伸应力层，其中低温沉积工艺的温度低于300摄氏度（℃）。 然后，进行高温退火处理，其中高温退火工艺的温度比低温沉积工艺的温度高至少150℃。 最后，在第一拉伸应力层上形成第二拉伸应力层，其中第一拉伸应力层的拉伸应力低于第二拉伸应力层的拉伸应力。

公开(公告)号：US20150004780A1

公开(公告)日：2015-01-01

申请号：US14490679

申请日：2014-09-19

申请人： UNITED MICROELECTRONICS CORP.

发明人： Tsun-Min Cheng ,  Min-Chuan Tsai ,  Chih-Chien Liu ,  Jen-Chieh Lin ,  Pei-Ying Li ,  Shao-Wei Wang ,  Mon-Sen Lin ,  Ching-Ling Lin

IPC分类号： H01L29/49 ,  H01L21/8234

CPC分类号： H01L29/4966 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4232 ,  H01L29/435 ,  H01L29/51 ,  H01L29/66045 ,  H01L29/66545 ,  H01L29/78

摘要： A metal gate structure located on a substrate includes a gate dielectric layer, a metal layer and a titanium aluminum nitride metal layer. The gate dielectric layer is located on the substrate. The metal layer is located on the gate dielectric layer. The titanium aluminum nitride metal layer is located on the metal layer.

摘要翻译： 位于基板上的金属栅极结构包括栅介质层，金属层和氮化铝钛金属层。 栅介质层位于衬底上。 金属层位于栅极电介质层上。 氮化铝钛金属层位于金属层上。

公开(公告)号：US20140117455A1

公开(公告)日：2014-05-01

申请号：US13662561

申请日：2012-10-29

申请人： UNITED MICROELECTRONICS CORP.

发明人： Chih-Chien Liu ,  Chun-Yuan Wu ,  Chin-Fu Lin ,  Chin-Cheng Chien ,  Chia-Lin Hsu

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/785 ,  H01L21/02225 ,  H01L21/764 ,  H01L27/11 ,  H01L29/66484 ,  H01L29/66795

摘要： A multigate field effect transistor includes two fin-shaped structures and a dielectric layer. The fin-shaped structures are located on a substrate. The dielectric layer covers the substrate and the fin-shaped structures. At least two voids are located in the dielectric layer between the two fin-shaped structures. Moreover, the present invention also provides a multigate field effect transistor process for forming said multigate field effect transistor including the following steps. Two fin-shaped structures are formed on a substrate. A dielectric layer covers the substrate and the two fin-shaped structures, wherein at least two voids are formed in the dielectric layer between the two fin-shaped structures.

摘要翻译： 多栅场效应晶体管包括两个鳍状结构和介电层。 鳍状结构位于基底上。 电介质层覆盖基板和鳍状结构。 在两个鳍状结构之间的电介质层中至少有两个空隙。 此外，本发明还提供了一种用于形成所述多栅极场效应晶体管的多栅场效应晶体管工艺，包括以下步骤。 在基板上形成两个鳍状结构。 介电层覆盖基板和两个鳍状结构，其中在两个鳍状结构之间的电介质层中形成至少两个空隙。