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25 条记录 (耗时 0.015 秒)

    Semiconductor packages and methods for making the same
    22.
    发明授权
    Semiconductor packages and methods for making the same 失效
    半导体封装及其制造方法

    公开(公告)号：US06858927B2

    公开(公告)日：2005-02-22

    申请号：US09971952

    申请日：2001-10-04

    申请人： Casey Prindiville ,  Tongbi Jiang ,  Bret Street

    发明人： Casey Prindiville ,  Tongbi Jiang ,  Bret Street

    IPC分类号： H01L21/56 ,  H01L21/66 ,  H01L23/48

    CPC分类号： H01L22/20 ,  H01L21/565 ,  H01L24/97 ,  H01L2224/4824 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  Y10T29/4913 ,  H01L2224/85 ,  H01L2924/00

    摘要： Semiconductor package support elements including cover members attached to one or more reject die sites are provided. Methods for making the support elements of the present invention and for making semiconductor packages using the same are also provided. Reject die sites on defective substrates of a support element are covered prior to the encapsulation process using a cover member. The cover member comprises, for example, pressure sensitive or temperature-activated tape, reject dies, or the like. The support elements and methods of the present invention virtually eliminate bleeding or flashing during encapsulation due to the presence of reject die sites. The support elements and methods of the present invention further ensure that functional dice are not sacrificed by being attached to reject die sites, thereby decreasing manufacturing costs while increasing yield of functional semiconductor packages.

    摘要翻译： 提供了包括附接到一个或多个废弃模具位置的盖构件的半导体封装支撑元件。 还提供了制造本发明的支撑元件和制造使用其的半导体封装件的方法。 在使用盖构件的封装工艺之前，覆盖支撑元件的有缺陷的基底上的模具位置。 盖构件包括例如压敏或温度活化的带，废模或类似物。 本发明的支撑元件和方法由于存在废弃模具位置而实际上消除了在封装期间的渗出或闪烁。 本发明的支撑元件和方法进一步确保功能性骰子不会被附着到废弃模具位置而牺牲，从而降低制造成本，同时提高功能性半导体封装的产量。

    Method for in-line testing of flip-chip semiconductor assemblies
    23.
    发明申请
    Method for in-line testing of flip-chip semiconductor assemblies 失效

    公开(公告)号：US20050024080A1

    公开(公告)日：2005-02-03

    申请号：US10927546

    申请日：2004-08-25

    申请人： Chad Cobbley ,  John VanNortwick ,  Bret Street ,  Tongbi Jiang

    发明人： Chad Cobbley ,  John VanNortwick ,  Bret Street ,  Tongbi Jiang

    IPC分类号： G01R1/04 ,  G01R31/26

    CPC分类号： G01R1/0483 ,  Y10T29/4913 ,  Y10T29/49144

    摘要： Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

    Method for in-line testing of flip-chip semiconductor assemblies
    24.
    发明申请
    Method for in-line testing of flip-chip semiconductor assemblies 失效

    公开(公告)号：US20050007141A1

    公开(公告)日：2005-01-13

    申请号：US10900609

    申请日：2004-07-27

    申请人： Chad Cobbley ,  John VanNortwick ,  Bret Street ,  Tongbi Jiang

    发明人： Chad Cobbley ,  John VanNortwick ,  Bret Street ,  Tongbi Jiang

    IPC分类号： G01R1/04 ,  G01R31/26

    CPC分类号： G01R1/0483 ,  Y10T29/4913 ,  Y10T29/49144

    摘要： Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.