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29 条记录 (耗时 0.026 秒)

    Method and apparatus for reducing non-snoop window of a cache controller by delaying host bus grant signal to the cache controller
    21.
    发明授权
    Method and apparatus for reducing non-snoop window of a cache controller by delaying host bus grant signal to the cache controller 失效
    通过将主机总线许可信号延迟到高速缓存控制器来减少高速缓存控制器的非窥探窗口的方法和装置

    公开(公告)号：US5463753A

    公开(公告)日：1995-10-31

    申请号：US955501

    申请日：1992-10-02

    申请人： Walter G. Fry ,  Jeff W. Wolford

    发明人： Walter G. Fry ,  Jeff W. Wolford

    IPC分类号： G06F12/08 ,  G06F13/36 ,  G06F13/14

    CPC分类号： G06F13/36 ,  G06F12/0831

    摘要： A method and apparatus which reduces the non-snoop window of a cache controller during certain operations to increase host bus efficiency. The cache controller requires a bus grant signal to perform cycles and cannot snoop cycles after the bus grant signal has been provided until the cycle completes. Cache interface logic monitors the cache controller for cycles that require either the expansion bus or the local I/O bus. When such a cycle is detected, the apparatus begins the cycle and does not assert the bus grant signal to the cache controller. The cache controller thus believes that the cycle has not yet begun and is thus able to perform other operations, such as snooping other host bus cycles. During this time, the cycle executes. When the read data is returned or when the write data reaches its destination, the interface logic provides the bus grant cycle to the cache controller at an appropriate time. By delaying the bus grant signal in this manner, the non-snoop window is reduced.

    摘要翻译： 一种在某些操作期间减少高速缓存控制器的非窥探窗口以增加主机总线效率的方法和装置。 高速缓存控制器需要总线授权信号来执行周期，并且在提供总线授权信号直到循环完成之后才能窥探周期。 缓存接口逻辑监控缓存控制器的周期，这些周期需要扩展总线或本地I / O总线。 当检测到这样的周期时，设备开始周期，并且不向总线授权信号断言到高速缓存控制器。 因此，高速缓存控制器认为该周期尚未开始，因此能够执行其他操作，例如窥探其他主机总线周期。 在此期间，循环执行。 当读取数据返回或写数据到达其目的地时，接口逻辑在适当的时间向缓存控制器提供总线授权周期。 通过以这种方式延迟总线授权信号，减少非窥视窗口。

    Method and apparatus for testing and debugging a tightly coupled mirrored processing system
    22.
    发明授权
    Method and apparatus for testing and debugging a tightly coupled mirrored processing system 失效
    用于测试和调试紧耦合镜像处理系统的方法和装置

    公开(公告)号：US5434997A

    公开(公告)日：1995-07-18

    申请号：US955980

    申请日：1992-10-02

    申请人： John A. Landry ,  Jeff W. Wolford ,  Walter G. Fry ,  Roger E. Tipley

    发明人： John A. Landry ,  Jeff W. Wolford ,  Walter G. Fry ,  Roger E. Tipley

    IPC分类号： G06F11/16 ,  G06F11/00 ,  G06F17/30

    CPC分类号： G06F11/1637 ,  G06F11/1679

    摘要： A method and apparatus for operating tightly coupled mirrored processors in a computer system. A plurality of CPU boards are coupled to a processor/memory bus, commonly called a host bus. Each CPU board includes a processor as well as various ports, timers, and interrupt controller logic local to the respective processor. The processors on one or more CPU boards are designated as master processors, with the processors on the remaining CPU boards being designated as mirroring or slave processors. A master processor has full access to the host bus and a second, multiplexed bus for read and write cycles, whereas the slave processors are prevented from writing to any bus. The slave processors compare write data and various control signals with that generated by its respective master processor for disparities. The system includes interrupt controller synchronization logic to synchronize interrupt requests as well as timer synchronization logic to synchronize the timers in each of the master and slave CPUs to guarantee that the master and slave CPUs operate in lockstep.

    摘要翻译： 一种用于在计算机系统中操作紧耦合的镜像处理器的方法和装置。 多个CPU板耦合到通常称为主机总线的处理器/存储器总线。 每个CPU板包括一个处理器以及各个处理器本地的各种端口，定时器和中断控制器逻辑。 一个或多个CPU板上的处理器被指定为主处理器，其余CPU板上的处理器被指定为镜像或从属处理器。 主处理器具有对主机总线的完全访问和用于读和写周期的第二复用总线，而从处理器被阻止写入任何总线。 从处理器将写入数据和各种控制信号与其相应的主处理器产生的差异进行比较。 该系统包括中断控制器同步逻辑，以同步中断请求以及定时器同步逻辑，以同步每个主CPU和从CPU的定时器，以保证主CPU和从CPU处于锁定状态。

    Methods and systems for a reference clock
    25.
    发明授权
    Methods and systems for a reference clock 有权
    参考时钟的方法和系统

    公开(公告)号：US07457904B2

    公开(公告)日：2008-11-25

    申请号：US11014409

    申请日：2004-12-16

    申请人： Richard S. Lin ,  Jeffrey K. Jeansonne ,  Walter G. Fry

    发明人： Richard S. Lin ,  Jeffrey K. Jeansonne ,  Walter G. Fry

    IPC分类号： G06F13/00 ,  G06F13/36 ,  G06F3/00 ,  G06F13/38 ,  G06F1/12 ,  G06F1/04

    CPC分类号： G06F1/12

    摘要： In at least some embodiments, a method comprises receiving an external card detection signal that indicates that a hot-pluggable card is coupled to a computer system and activating at least one reference clock signal of a scalable reference clock platform based on the external card detection signal. The method further comprises synchronizing clock signals embedded in data packets transmitted between the hot-pluggable card and the computer system with another clock signal bases on the at least one reference clock signal.

    摘要翻译： 在至少一些实施例中，一种方法包括接收外部卡片检测信号，该信号指示热插拔卡耦合到计算机系统，并基于外部卡检测信号激活可伸缩参考时钟平台的至少一个参考时钟信号 。 该方法还包括基于至少一个参考时钟信号，将嵌入在热插拔卡和计算机系统之间传输的数据分组中的时钟信号与另一个时钟信号同步。

    Electronic device thermal management system and method
    26.
    发明申请
    Electronic device thermal management system and method 有权
    电子设备热管理系统及方法

    公开(公告)号：US20080269954A1

    公开(公告)日：2008-10-30

    申请号：US11799185

    申请日：2007-04-30

    申请人： Jeffrey A. Lev ,  Jeffrey Kevin Jeansonne ,  Walter G. Fry

    发明人： Jeffrey A. Lev ,  Jeffrey Kevin Jeansonne ,  Walter G. Fry

    IPC分类号： G05D23/00

    CPC分类号： G05D23/19

    摘要： An electronic device thermal management system comprising a thermal management controller configured to maintain a temperature level within a housing of an electronic device based on a signal indicative of a temperature of at least a portion of a wall of the housing of the electronic device.

    摘要翻译： 一种电子设备热管理系统，包括热管理控制器，其被配置为基于指示电子设备的壳体的壁的至少一部分的温度的信号来将电子设备的壳体内的温度水平维持在电子设备的壳体内。

    Enhanced PCI clock control architecture
    27.
    发明授权
    Enhanced PCI clock control architecture 失效
    增强的PCI时钟控制架构

    公开(公告)号：US06496938B1

    公开(公告)日：2002-12-17

    申请号：US09502326

    申请日：2000-02-11

    申请人： Walter G. Fry ,  Kenneth W. Stufflebeam ,  Paul C. Stanley

    发明人： Walter G. Fry ,  Kenneth W. Stufflebeam ,  Paul C. Stanley

    IPC分类号： G06F132

    CPC分类号： G06F1/3237 ,  G06F1/3203 ,  G06F1/3253 ,  G06F1/3287 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D10/171

    摘要： A clock control technique allows reducing the power consumption of devices connected to a computer bus. Individual idle devices can be disconnected from the bus clock by a device clock controller and placed in a low-power state without waiting for all devices on the bus to go idle. When individual devices are idle, transactions on the bus are monitored and unclaimed transactions are claimed by the device clock controller, which then forces a retry of the transaction and reconnects the clock to the idle devices. This brings these devices from the low-power state to a full power state, where they are capable of claiming the transaction when it is retried.

    摘要翻译： 时钟控制技术允许降低连接到计算机总线的设备的功耗。 单个空闲设备可以通过设备时钟控制器与总线时钟断开连接，并处于低功耗状态，而无需等待总线上的所有设备空闲。 当单个设备空闲时，监控总线上的事务，并且设备时钟控制器要求无人认领的事务，然后强制重试事务并将时钟重新连接到空闲设备。 这使得这些设备从低功耗状态转变为全功率状态，当它们被重试时，它们能够声明该事务。

    Computer system with support for a subtractive agent on the secondary side of a PCI-to-PCI bridge
    28.
    发明授权
    Computer system with support for a subtractive agent on the secondary side of a PCI-to-PCI bridge 失效
    计算机系统，支持PCI-PCI桥接二次侧的减法器

    公开(公告)号：US06230227B1

    公开(公告)日：2001-05-08

    申请号：US09209939

    申请日：1998-12-11

    申请人： Walter G. Fry ,  Todd J. Deschepper ,  James R. Reif

    发明人： Walter G. Fry ,  Todd J. Deschepper ,  James R. Reif

    IPC分类号： G06F1300

    CPC分类号： G06F13/404

    摘要： A computer system for supporting a subtractive agent on a secondary PCI bus is provided. A bridge resides between a primary PCI bus and a secondary PCI bus. Where both a master device and a target device reside on the secondary PCI bus, the bridge employs one of two protocols to permit successful completion of the transaction. The protocol used depends upon the type of transaction sought by the master device. Once the subtractive agent is identified by address, the bridge keeps track of its location. Thus, further operations targeting the subtractive agent run without requiring either protocol to be used. Further, the need for a specialized signaling protocol to access the subtractive agent is avoided.

    摘要翻译： 提供了用于在辅助PCI总线上支持减法器的计算机系统。 桥接器位于主PCI总线和辅助PCI总线之间。 在主设备和目标设备驻留在辅助PCI总线上的情况下，桥接器使用两种协议之一来允许成功完成事务。 使用的协议取决于主设备所寻求的事务类型。 一旦通过地址识别减法器，桥就会跟踪其位置。 因此，靶向减法器的进一步操作不需要使用任何协议。 此外，避免需要专门的信令协议来访问减法器。