公开(公告)号：US08416785B2

公开(公告)日：2013-04-09

申请号：US12764193

申请日：2010-04-21

申请人： Phillip Rogers Hillier, III ,  David Alan Shedivy ,  Kenneth Michael Valk ,  Bruce Marshall Walk

发明人： Phillip Rogers Hillier, III ,  David Alan Shedivy ,  Kenneth Michael Valk ,  Bruce Marshall Walk

IPC分类号： H04L12/28

CPC分类号： H04L47/34 ,  H04L45/245 ,  H04L49/552

摘要： A method and circuit for implementing multiple active paths between source and destination devices in an interconnect system while removing ghost packets, and a design structure on which the subject circuit resides are provided. Each packet includes a generation ID and is assigned an End-to-End (ETE) sequence number in the source interconnect chip that represents the packet position in an ordered packet stream from the source device. The packets are transmitted from a source interconnect chip source to a destination interconnect chip on the multiple active paths. The generation ID of a received packet is compared with a current generation ID at a destination interconnect chip to validate packet acceptance. The destination interconnect chip uses the ETE sequence numbers to reorder the accepted received packets into the correct order before sending the packets to the destination device.

摘要翻译： 一种用于在去除重影分组的同时在互连系统中实现源和目的设备之间的多个活动路径的方法和电路，以及提供了所述主题电路所在的设计结构。 每个分组包括生成ID，并且在源互连芯片中分配表示来自源设备的有序分组流中的分组位置的端到端（ETE）序列号。 分组从源互连芯片源传输到多个主动路径上的目的地互连芯片。 将接收到的分组的生成ID与目的地互连芯片上的当前生成ID进行比较，以验证分组接受。 目的互连芯片在将数据包发送到目标设备之前，使用ETE序列号将接收的接收数据包重新排序为正确的顺序。

公开(公告)号：US08185662B2

公开(公告)日：2012-05-22

申请号：US12719214

申请日：2010-03-08

申请人： Kenneth Michael Valk

发明人： Kenneth Michael Valk

IPC分类号： G06F15/16

CPC分类号： G06F15/16

摘要： A method and circuit for implementing enhanced transport layer flow control, and a design structure on which the subject circuit resides are provided. The transport layer provides multiple virtual lanes to application layers, and provides buffering and credit control for the multiple virtual lanes. A source transport layer sends a credit request message to a destination transport layer for an outstanding packets transmission. The packets are sent only responsive to the credit request being granted by the destination transport layer. Respective switch and link layer are constructed to support only a single virtual lane, regardless of how many virtual lanes are supported at the application and transport layers. As a result, the routing, buffering, and flow control at the respective switch and link layer are simplified.

摘要翻译： 一种用于实现增强的传输层流控制的方法和电路，以及设置有该主题电路所在的设计结构。 传输层为应用层提供多个虚拟通道，并为多个虚拟通道提供缓冲和信用控制。 源传输层向目的地传输层发送信用请求消息，用于未完成的分组传输。 仅响应于目的地传输层授予的信用请求而发送分组。 不管开关和链路层是如何支持单个虚拟通道，不管应用层和传输层支持多少个虚拟通道。 结果，简化了各个交换机和链路层的路由，缓冲和流控制。

公开(公告)号：US20110228783A1

公开(公告)日：2011-09-22

申请号：US12727545

申请日：2010-03-19

申请人： William Thomas Flynn ,  Philip Rogers Hillier, III ,  David Alan Shedivy ,  Kenneth Michael Valk

发明人： William Thomas Flynn ,  Philip Rogers Hillier, III ,  David Alan Shedivy ,  Kenneth Michael Valk

IPC分类号： H04L12/56

CPC分类号： G06F13/4022 ,  G06F2213/0026

摘要： A method and circuit for implementing ordered and reliable transfer of packets while spraying packets over multiple links, and a design structure on which the subject circuit resides are provided. Each source interconnect chip maintains a spray mask including multiple available links for each destination chip for spraying packets across multiple links of a local rack interconnect system. Each packet is assigned an End-to-End (ETE) sequence number in the source interconnect chip that represents the packet position in an ordered packet stream from the source device. The destination interconnect chip uses the ETE sequence numbers to reorder the received sprayed packets into the correct order before sending the packets to the destination device.

摘要翻译： 一种用于在通过多个链路喷射分组时实现分组的有序和可靠传送的方法和电路，并且提供了主题电路所在的设计结构。 每个源互连芯片保持喷射掩模，其包括用于每个目的地芯片的多个可用链路，用于在本地机架互连系统的多个链路上喷射分组。 每个数据包被分配在源互连芯片中的端到端（ETE）序列号，其表示来自源设备的有序分组流中的分组位置。 目的互连芯片在将数据包发送到目标设备之前，使用ETE序列号将接收到的喷射数据包重新排序为正确的顺序。

公开(公告)号：US20110219139A1

公开(公告)日：2011-09-08

申请号：US12719214

申请日：2010-03-08

申请人： Kenneth Michael Valk

发明人： Kenneth Michael Valk

IPC分类号： G06F15/16

CPC分类号： G06F15/16

摘要： A method and circuit for implementing enhanced transport layer flow control, and a design structure on which the subject circuit resides are provided. The transport layer provides multiple virtual lanes to application layers, and provides buffering and credit control for the multiple virtual lanes. A source transport layer sends a credit request message to a destination transport layer for an outstanding packets transmission. The packets are sent only responsive to the credit request being granted by the destination transport layer. Respective switch and link layer are constructed to support only a single virtual lane, regardless of how many virtual lanes are supported at the application and transport layers. As a result, the routing, buffering, and flow control at the respective switch and link layer are simplified.

摘要翻译： 一种用于实现增强的传输层流控制的方法和电路，以及设置有该主题电路所在的设计结构。 传输层为应用层提供多个虚拟通道，并为多个虚拟通道提供缓冲和信用控制。 源传输层向目的地传输层发送信用请求消息，用于未完成的分组传输。 仅响应于目的地传输层授予的信用请求而发送分组。 不管开关和链路层是如何支持单个虚拟通道，不管应用层和传输层支持多少个虚拟通道。 结果，简化了各个交换机和链路层的路由，缓冲和流控制。

公开(公告)号：US07996621B2

公开(公告)日：2011-08-09

申请号：US11776731

申请日：2007-07-12

申请人： Jeffrey Douglas Brown ,  Russell Dean Hoover ,  Eric Oliver Mejdrich ,  Kenneth Michael Valk

发明人： Jeffrey Douglas Brown ,  Russell Dean Hoover ,  Eric Oliver Mejdrich ,  Kenneth Michael Valk

IPC分类号： G06F12/12

CPC分类号： G06F12/0895 ,  Y02D10/13

摘要： According to embodiments of the invention, a step value and a step-interval cache coherency protocol may be used to update and invalidate data stored within cache memory. A step value may be an integer value and may be stored within a cache directory entry associated with data in the memory cache. Upon reception of a cache read request, along with the normal address comparison to determine if the data is located within the cache a current step value may be compared with the stored step value to determine if the data is current. If the step values match, the data may be current and a cache hit may occur. However, if the step values do not match, the requested data may be provided from another source. Furthermore, an application may update the current step value to invalidate old data stored within the cache and associated with a different step value.

摘要翻译： 根据本发明的实施例，可以使用步长值和步进间隔高速缓存一致性协议来更新和使存储在高速缓冲存储器中的数据无效。 步数值可以是整数值，并且可以存储在与存储器高速缓存中的数据相关联的高速缓存目录条目中。 在接收到缓存读取请求时，连同正常地址比较以确定数据是否位于高速缓存内，可以将当前步长值与存储的步长值进行比较，以确定数据是否为当前值。 如果步数值匹配，数据可能是当前的，并且可能会发生高速缓存命中。 然而，如果步骤值不匹配，则可以从另一个源提供所请求的数据。 此外，应用程序可以更新当前步骤值以使存储在高速缓存中并与不同步长值相关联的旧数据无效。