公开(公告)号：US08716100B2

公开(公告)日：2014-05-06

申请号：US13212922

申请日：2011-08-18

申请人： Kuo-Chyuan Tzeng ,  Luan C. Tran ,  Chen-Jong Wang ,  Kuo-Chi Tu ,  Hsiang-Fan Lee

发明人： Kuo-Chyuan Tzeng ,  Luan C. Tran ,  Chen-Jong Wang ,  Kuo-Chi Tu ,  Hsiang-Fan Lee

IPC分类号： H01L21/20

CPC分类号： H01L28/86 ,  H01L23/5223 ,  H01L28/40 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of MIM capacitors may be embedded into a thick IMD layer with enough thickness (e.g., 10 KŘ30 KÅ) to get high capacitance, which may be on top of a thinner IMD layer. MIM capacitors may be formed among three adjacent metal layers which have two thick IMD layers separating the three adjacent metal layers. Materials such as TaN or TiN are used as bottom/top electrodes & Cu barrier. The metal layer above the thick IMD layer may act as the top electrode connection. The metal layer under the thick IMD layer may act as the bottom electrode connection. The capacitor may be of different shapes such as cylindrical shape, or a concave shape. Many kinds of materials (Si3N4, ZrO2, HfO2, BST . . . etc) can be used as the dielectric material. The MIM capacitors are formed by one or two extra masks while forming other non-capacitor logic of the circuit.

摘要翻译： MIM电容器的实施例可以嵌入到具有足够厚度（例如，10K〜30K）的厚IMD层中以获得高电容，其可以在更薄的IMD层之上。 可以在三个相邻的金属层之间形成MIM电容器，这两个相邻的金属层具有两个分开三个相邻金属层的厚的IMD层。 诸如TaN或TiN的材料用作底部/顶部电极和Cu屏障。 厚IMD层上方的金属层可以用作顶部电极连接。 厚IMD层下面的金属层可以用作底部电极连接。 电容器可以是不同的形状，例如圆柱形或凹形。 可以使用多种材料（Si3N4，ZrO2，HfO2，BST等）作为介电材料。 MIM电容器由一个或两个额外的掩模形成，同时形成电路的其他非电容器逻辑。

公开(公告)号：US20130043560A1

公开(公告)日：2013-02-21

申请号：US13212922

申请日：2011-08-18

申请人： Kuo-Chyuan Tzeng ,  Luan C. Tran ,  Chen-Jong Wang ,  Kuo-Chi Tu ,  Hsiang-Fan Lee

发明人： Kuo-Chyuan Tzeng ,  Luan C. Tran ,  Chen-Jong Wang ,  Kuo-Chi Tu ,  Hsiang-Fan Lee

IPC分类号： H01L27/06 ,  H01L21/02

CPC分类号： H01L28/86 ,  H01L23/5223 ,  H01L28/40 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of MIM capacitors may be embedded into a thick IMD layer with enough thickness (e.g., 10 KŘ30 KÅ) to get high capacitance, which may be on top of a thinner IMD layer. MIM capacitors may be formed among three adjacent metal layers which have two thick IMD layers separating the three adjacent metal layers. Materials such as TaN or TiN are used as bottom/top electrodes & Cu barrier. The metal layer above the thick IMD layer may act as the top electrode connection. The metal layer under the thick IMD layer may act as the bottom electrode connection. The capacitor may be of different shapes such as cylindrical shape, or a concave shape. Many kinds of materials (Si3N4, ZrO2, HfO2, BST . . . etc) can be used as the dielectric material. The MIM capacitors are formed by one or two extra masks while forming other non-capacitor logic of the circuit.

摘要翻译： MIM电容器的实施例可以嵌入到具有足够厚度（例如，10K〜30K）的厚IMD层中以获得高电容，其可以在更薄的IMD层之上。 可以在三个相邻的金属层之间形成MIM电容器，这两个相邻的金属层具有两个分开三个相邻金属层的厚的IMD层。 诸如TaN或TiN的材料用作底部/顶部电极和Cu屏障。 厚IMD层上方的金属层可以用作顶部电极连接。 厚IMD层下面的金属层可以用作底部电极连接。 电容器可以是不同的形状，例如圆柱形或凹形。 可以使用多种材料（Si3N4，ZrO2，HfO2，BST等）作为介电材料。 MIM电容器由一个或两个额外的掩模形成，同时形成电路的其他非电容器逻辑。

公开(公告)号：US20080116496A1

公开(公告)日：2008-05-22

申请号：US11809642

申请日：2007-06-01

申请人： Kuo-Chyuan Tzeng ,  Kuo-Chiang Ting ,  Chen-Jong Wang ,  Min-Hsiung Chiang ,  Chih-Yang Pai

发明人： Kuo-Chyuan Tzeng ,  Kuo-Chiang Ting ,  Chen-Jong Wang ,  Min-Hsiung Chiang ,  Chih-Yang Pai

IPC分类号： H01L27/108

CPC分类号： H01L27/105 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1116

摘要： A novel SOC structure and method of making the same are provided. An SOC comprises a logic region, an SRRM and a DRAM region. The storage capacitor in a DRAM cell is formed in the first dielectric layer in an MIM (metal-insulator-metal) configuration, having a large vertical surface area. A butted contact, formed in said first dielectric layer, comprises a bottom portion abutting a first and second conductive region in an SRAM cell, and a vertically aligned top portion coupled to a first metal layer. The top portion has a substantially larger depth than that of the bottom portion, while substantially smaller in size. Forming this SOC structure does not require adding complex, error-prone additional processing steps on an existing CMOS manufacturing process, thus having little impact on the overall SOC product yield.

摘要翻译： 提供了一种新颖的SOC结构及其制造方法。 SOC包括逻辑区域，SRRM和DRAM区域。 金属 - 绝缘体 - 金属）构造中的DRAM单元中的存储电容器形成在第一介电层中，具有大的垂直表面积。 形成在所述第一电介质层中的对接触点包括邻接SRAM单元中的第一和第二导电区域的底部以及耦合到第一金属层的垂直对齐的顶部。 顶部具有比底部大的深度大得多的深度，而其尺寸基本上更小。 形成这种SOC结构不需要在现有的CMOS制造工艺上增加复杂的，容易出错的附加处理步骤，因此对整个SOC产品产量几乎没有影响。

公开(公告)号：US06670664B1

公开(公告)日：2003-12-30

申请号：US10279809

申请日：2002-10-22

申请人： Kuo-Chyuan Tzeng ,  Dennis J. Sinitsky ,  Chen-Jong Wang ,  Wen-Chaun Chiang

发明人： Kuo-Chyuan Tzeng ,  Dennis J. Sinitsky ,  Chen-Jong Wang ,  Wen-Chaun Chiang

IPC分类号： H01L27108

CPC分类号： H01L27/10805 ,  H01L27/10873

摘要： A random access memory cell and a method for fabrication thereof provide a field effect transistor device laterally adjoining a metal oxide semiconductor capacitor device, each formed within an active region of a semiconductor substrate. Within the random access memory cell and method: (1) a single fluorinated silicon oxide layer of a single thickness serves as both a gate dielectric layer within the field effect transistor device and a capacitor dielectric layer within the metal oxide semiconductor capacitor device; and (2) a channel region within the field effect transistor device has a different threshold voltage adjusting dopant concentration in comparison with a semiconductor plate region within the metal oxide semiconductor capacitor device. The random access memory cell is fabricated with enhanced performance.

摘要翻译： 随机存取存储单元及其制造方法提供横向邻接金属氧化物半导体电容器器件的场效应晶体管器件，每个形成在半导体衬底的有源区内。 在随机存取存储器单元和方法中：（1）单个厚度的单个氟化硅氧化物层用作场效应晶体管器件内的栅极电介质层和金属氧化物半导体电容器器件内的电容器电介质层; 和（2）场效应晶体管器件内的沟道区域与金属氧化物半导体电容器件内的半导体板区域相比具有不同的阈值电压调整掺杂剂浓度。 该随机存取存储器单元以增强的性能制造。

公开(公告)号：US06661049B2

公开(公告)日：2003-12-09

申请号：US09947793

申请日：2001-09-06

申请人： Kuo-Chyuan Tzeng ,  Chen-Jong Wang ,  Chung-Wei Chang

发明人： Kuo-Chyuan Tzeng ,  Chen-Jong Wang ,  Chung-Wei Chang

IPC分类号： H01L29772

CPC分类号： H01L27/10861 ,  H01L27/10829 ,  H01L27/10867 ,  H01L28/91 ,  H01L29/945

摘要： Within a method for fabricating a capacitor structure, and a capacitor structure fabricated employing the method, there is formed within an isolation region adjoining an active region of a semiconductor substrate a laterally asymmetric trench which leaves exposed an upper sidewall portion of the active region of the semiconductor substrate. There is then formed within the laterally asymmetric trench a capacitor node layer which contacts the exposed upper sidewall portion of the active region of the semiconductor substrate and extends above the active region of the semiconductor substrate. The capacitor may be a storage capacitor with increased capacitance fabricated within a memory cell structure of decreased dimensions.

公开(公告)号：US06338998B1

公开(公告)日：2002-01-15

申请号：US09713652

申请日：2000-11-15

申请人： Chen-Jong Wang ,  Chen-Yong Lin ,  Kevin Chiang

发明人： Chen-Jong Wang ,  Chen-Yong Lin ,  Kevin Chiang

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L27/10811 ,  H01L27/10873

摘要： Within a method for fabricating an embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrication there is formed contacting a second source/drain region within a field effect transistor (FET) memory semiconductor integrated circuit microelectronic fabrication device a storage capacitor prior to forming within a field effect transistor (FET) logic semiconductor integrated circuit microelectronic fabrication device a pair of first source/drain regions. By employing such a process ordering, the field effect transistor (FET) logic semiconductor integrated circuit microelectronic device, and the embedded dynamic random access memory (DRAM) semiconductor integrated circuit microelectronic fabrication, are fabricated with enhanced performance.

摘要翻译： 在用于制造嵌入式动态随机存取存储器（DRAM）半导体集成电路微电子制造的方法中，形成在场效应晶体管（FET）存储器半导体集成电路微电子制造器件中的第二源极/漏极区域之前形成的存储电容器 在场效应晶体管（FET）逻辑半导体集成电路微电子制造装置内有一对第一源/漏区。 通过采用这种处理顺序，以增强的性能制造场效应晶体管（FET）逻辑半导体集成电路微电子器件以及嵌入式动态随机存取存储器（DRAM）半导体集成电路微电子制造。

公开(公告)号：US06265301B1

公开(公告)日：2001-07-24

申请号：US09310258

申请日：1999-05-12

申请人： Jin-Yuan Lee ,  Chen-Jong Wang

发明人： Jin-Yuan Lee ,  Chen-Jong Wang

IPC分类号： H01L214763

CPC分类号： H01L21/2885 ,  H01L21/288 ,  H01L21/76885

摘要： A process for forming metal interconnect structures, and metal via structures, using electroplating, or electroless plating procedures, has been developed. The process features the use of disposable conductive layers, used as seed layers for the plating procedures. After formation of the desired metal structures, on the portion of seed layer, exposed in an opening in the photoresist shape, the photoresist shape, and the underlying portion of the disposable conductive layer, are removed, resulting in the desired metal structures.

摘要翻译： 已经开发了用于形成金属互连结构的方法，以及使用电镀或无电镀方法的金属通孔结构。 该方法的特征在于使用一次性导电层，用作电镀步骤的籽晶层。 在形成期望的金属结构之后，在种子层的暴露在光致抗蚀剂形状的开口中，光致抗蚀剂形状和一次性导电层的下面部分被去除，从而产生所需的金属结构。

公开(公告)号：US06201273B1

公开(公告)日：2001-03-13

申请号：US09225668

申请日：1999-01-05

申请人： Chen-Jong Wang ,  Mong-Song Liang

发明人： Chen-Jong Wang ,  Mong-Song Liang

IPC分类号： H01L27108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/87 ,  H01L28/91

摘要： A method and structure is described for a DRAM cell having a double wall tub shaped capacitor. The structure of the capacitor has two embodiments: a double wall tub shaped capacitor and a double wall cup shaped capacitor. In a first embodiment for the tub shaped capacitor, the method comprises using two masks to form a tub shaped hole partial through an insulating layer and a concentric contact hole over the source. A polysilicon layer is formed over the insulating layer. Oxide spacers are formed on the sidewalls of the tub shaped hole. The polysilicon layer is patterned to separate adjacent electrodes. Next, a polysilicon inner wall is formed on the spacer sidewalls. The oxide spacers are then removed. The dielectric and top electrode are formed next thus completing the double wall tub shaped capacitor. The second embodiment for forming the cup shaped capacitor comprises forming an insulating layer the substrate surface and forming a photoresist layer with an opening over a source region. The insulating layer is isotropically etched through the opening to form a cup shaped cavity. Next, the insulating layer is anisotropically etch through the opening to form a contact opening exposing the source. A polysilicon layer is formed filling the contact hole and the cup shaped cavity. Oxide and polysilicon spacers are sequentially formed on the sidewalls of the cylindrical hole. The insulating layer and oxide spacers are then removed. A capacitor dielectric and a top electrode are formed over the storage electrode to complete the double wall cup shaped capacitor.

摘要翻译： 描述了具有双壁桶形电容器的DRAM单元的方法和结构。 电容器的结构具有两个实施例：双壁桶状电容器和双壁杯形电容器。 在用于桶形电容器的第一实施例中，该方法包括使用两个掩模以在源极上部分地穿过绝缘层和同心接触孔形成盆形孔。 绝缘层上形成多晶硅层。 氧化物间隔件形成在桶形孔的侧壁上。 图案化多晶硅层以分离相邻的电极。 接下来，在间隔壁侧壁上形成多晶硅内壁。 然后除去氧化物间隔物。 接下来形成电介质和顶电极，从而完成双壁桶形电容器。 用于形成杯形电容器的第二实施例包括在衬底表面上形成绝缘层并在源极区域上形成具有开口的光致抗蚀剂层。 绝缘层通过开口进行各向同性蚀刻，形成杯形腔。 接下来，绝缘层通过开口各向异性地蚀刻以形成暴露源的接触开口。 形成填充接触孔和杯形腔的多晶硅层。 氧化物和多晶硅间隔物依次形成在圆柱形孔的侧壁上。 然后去除绝缘层和氧化物间隔物。 在存储电极上形成电容器电介质和顶电极以完成双壁杯形电容器。

公开(公告)号：US6025279A

公开(公告)日：2000-02-15

申请号：US86824

申请日：1998-05-29

申请人： Min-Hsiung Chiang ,  Chen-Jong Wang ,  Jenn Ming Huang

发明人： Min-Hsiung Chiang ,  Chen-Jong Wang ,  Jenn Ming Huang

IPC分类号： H01L21/3105 ,  H01L21/314 ,  H01L21/02

CPC分类号： H01L21/31053

摘要： A method of rapid thermal annealing (RTA) a TEOS oxide layer 50 that underlies a silicon nitride stop layer 60. The RTA of the TEOS-Oxide ILD layer 50 prevents the nitride stop layer 60 and oxide ILD layer 50 from peeling in subsequent thermal steps. The process comprises providing a semiconductor structure 10 with an uneven surface; forming an interlevel dielectric layer 50 composed of PE-TEOS oxide over the structure 10; rapid thermal annealing (RTA) the third interlevel dielectric layer 50 at a temperature between about 850 and 1015.degree. C. for a time between about 10 and 50 seconds; depositing a silicon nitride layer 60 over the third interlevel dielectric layer 50; and planarizing the silicon nitride layer 60 and the third interlevel dielectric layer 50.

摘要翻译： 快速热退火（RTA）在氮化硅阻挡层60下面的TEOS氧化物层50的方法.TEOS-氧化物ILD层50的RTA防止氮化物阻挡层60和氧化物ILD层50在随后的热步骤中剥离 。 该方法包括提供具有不平坦表面的半导体结构10; 在结构10上形成由PE-TEOS氧化物构成的层间电介质层50; 快速热退火（RTA）第三层间介电层50在约850至1015℃的温度下约10至50秒之间的时间; 在第三层间介质层50上沉积氮化硅层60; 并且平坦化氮化硅层60和第三层间电介质层50。

公开(公告)号：US5607879A

公开(公告)日：1997-03-04

申请号：US496019

申请日：1995-06-28

申请人： Shou-Gwo Wuu ,  Chen-Jong Wang ,  Mong-Song Liang ,  Chung-Hui Su

发明人： Shou-Gwo Wuu ,  Chen-Jong Wang ,  Mong-Song Liang ,  Chung-Hui Su

IPC分类号： H01L21/311 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L21/28

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/76801 ,  H01L23/485 ,  H01L2924/0002

摘要： A method for fabricating buried metal plug structures for multi-polysilicon layer interconnects and for concurrently making metal plugs on semiconductor integrated circuits, such as DRAM and SRAM, was achieved. The method involved forming contact opening in an insulating layer over opening in a patterned polysilicon layer. The opening in the polysilicon layer aligned over source/drain contact areas on the substrate and providing a means for forming self-aligned contact openings. Buried metal plugs in the contact openings form interconnects between the polysilicon layer and the source/drains. And, by merging the process steps, concurrently forming metal plug interconnects for contacts to semiconductor devices and first level metal. The process is applicable to the formation of bit line contacts on DRAM and SRAM circuits and simultaneously form the peripheral contact on the chip.