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29 条记录 (耗时 0.035 秒)

    Dual zone, fault tolerant computer system with error checking in I/O writes
    23.
    发明授权
    Dual zone, fault tolerant computer system with error checking in I/O writes 失效
    双区域，容错计算机系统，在I / O写入中进行错误检查

    公开(公告)号：US5005174A

    公开(公告)日：1991-04-02

    申请号：US489751

    申请日：1990-02-26

    申请人： William F. Bruckert ,  Thomas D. Bissett

    发明人： William F. Bruckert ,  Thomas D. Bissett

    IPC分类号： G06F11/18 ,  G06F1/12 ,  G06F1/16 ,  G06F11/00 ,  G06F11/08 ,  G06F11/10 ,  G06F11/14 ,  G06F11/16 ,  G06F11/20 ,  G06F11/22

    CPC分类号： G06F1/12 ,  G06F1/16 ,  G06F11/1633 ,  G06F11/1645 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/1679 ,  G06F11/076 ,  G06F11/0796 ,  G06F11/08 ,  G06F11/10 ,  G06F11/1044 ,  G06F11/14 ,  G06F11/22 ,  G06F11/2205 ,  G06F2201/88

    摘要： A fault tolerant computer system having a first processing system which includes a first data processor for executing a series of data processing instructions. A first data output terminal outputs data from the first processing system. A second processing system, substantially identical to the first processing system, operates independently from the first processing system. The second processing system includes a second data processor for executing the series of data processing instructions in the same sequence as the first data processor. It also includes a second data output terminal for outputting data from the second processing system. A synchronizing device is coupled to the first and second data processors for maintaining the execution of the series of data processing instructions by the first and second processing systems in synchronism. Fault detection devices are coupled to the first and second data output terminals for comparing the data output from the first processing system with the data output from the second processing system. The fault detection devices identify the presence of an error when the data output from the first processing system at the first output terminal is different from the data output from the second processing system at the second output terminal.

    摘要翻译： 一种具有第一处理系统的容错计算机系统，其包括用于执行一系列数据处理指令的第一数据处理器。 第一数据输出端子从第一处理系统输出数据。 基本上与第一处理系统相同的第二处理系统独立于第一处理系统工作。 第二处理系统包括用于以与第一数据处理器相同的顺序执行一系列数据处理指令的第二数据处理器。 它还包括用于从第二处理系统输出数据的第二数据输出端。 同步装置耦合到第一和第二数据处理器，用于同步地由第一和第二处理系统维持一系列数据处理指令的执行。 故障检测装置耦合到第一和第二数据输出端，用于将从第一处理系统输出的数据与从第二处理系统输出的数据进行比较。 当从第一输出端子的第一处理系统输出的数据与在第二输出端子处从第二处理系统输出的数据不同时，故障检测装置识别出现错误。

    Fault tolerant computing systems using checkpoints
    24.
    发明授权
    Fault tolerant computing systems using checkpoints 有权
    使用检查点的容错计算系统

    公开(公告)号：US08812907B1

    公开(公告)日：2014-08-19

    申请号：US13186087

    申请日：2011-07-19

    申请人： Thomas D. Bissett ,  Paul A. Leveille ,  Ted M. Lin ,  Jerry Melnick ,  Angel L. Pagan ,  Glenn A. Tremblay

    发明人： Thomas D. Bissett ,  Paul A. Leveille ,  Ted M. Lin ,  Jerry Melnick ,  Angel L. Pagan ,  Glenn A. Tremblay

    IPC分类号： G06F11/00

    CPC分类号： G06F11/1484 ,  G06F11/2038 ,  G06F11/2097

    摘要： A computer system configured to provide fault tolerance includes a first host system and a second host system. The first host system is programmed to monitor a number of portions of memory of the first host system that have been modified by a guest running on the first host system and, upon determining that the number of portions exceeds a threshold level, determine that a checkpoint needs to be created. Upon determining that the checkpoint needs to be created, operation of the guest is paused and checkpoint data is generated. After generating the checkpoint data, operation of the guest is resumed while the checkpoint data is transmitted to the second host system.

    摘要翻译： 被配置为提供容错的计算机系统包括第一主机系统和第二主机系统。 第一主机系统被编程为监视由第一主机系统上运行的客户机修改的第一主机系统的多个部分部分，并且在确定部件数量超过阈值电平时，确定检查点 需要创建。 在确定需要创建检查点时，暂停客户机的操作并生成检查点数据。 在产生检查点数据之后，当检查点数据被发送到第二主机系统时，恢复访客的操作。

    Fault resilient/fault tolerant computing
    26.
    发明授权
    Fault resilient/fault tolerant computing 有权
    故障恢复/容错计算

    公开(公告)号：US06279119B1

    公开(公告)日：2001-08-21

    申请号：US09190269

    申请日：1998-11-13

    申请人： Thomas D. Bissett ,  Paul A. Leveille ,  Erik Muench

    发明人： Thomas D. Bissett ,  Paul A. Leveille ,  Erik Muench

    IPC分类号： G06F1100

    CPC分类号： G06F11/1633 ,  G06F11/1641 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/1679 ,  G06F11/1687 ,  G06F11/1691

    摘要： A fault tolerant/fault resilient computer system includes at least two compute elements connected to at least one controller. Each compute element has clocks that operate asynchronously to clocks of the other compute elements. The compute elements operate in a first mode in which the compute elements each execute a first stream of instructions in emulated clock lockstep, and in a second mode in which the compute elements each execute a second stream of instructions in instruction lockstep. Each compute element may be a multi-processor compute element.

    摘要翻译： 容错/故障恢复计算机系统包括连接到至少一个控制器的至少两个计算元件。 每个计算元件具有与其他计算元素的时钟异步运行的时钟。 计算元件以第一模式工作，其中计算元件各自在仿真时钟锁步骤中执行指令的第一流，并且在第二模式中，计算元件在指令锁定步骤中每个执行第二指令流。 每个计算元件可以是多处理器计算元件。

    Memory device with transfer of ECC signals on time division multiplexed bidirectional lines
    29.
    发明授权
    Memory device with transfer of ECC signals on time division multiplexed bidirectional lines 失效
    具有时分复用双向线上ECC信号传输的存储器件

    公开(公告)号：US5048022A

    公开(公告)日：1991-09-10

    申请号：US388323

    申请日：1989-08-01

    申请人： Thomas D. Bissett ,  Norbert H. Riegelhaupt ,  Mitch Berkson

    发明人： Thomas D. Bissett ,  Norbert H. Riegelhaupt ,  Mitch Berkson

    IPC分类号： G06F12/16 ,  G06F11/10 ,  G06F11/16

    CPC分类号： G06F11/1044 ,  G06F11/10 ,  G06F11/16

    摘要： A memory for storing data in a computer system. Integrity of data transferred to or from a memory array is monitored by transferring two sets of EDC or ECC data corresponding to a longword of data between the memory array and two separate memory controllers. The probability of an undetected error is very low because the two sets of EDC or ECC data are compared to ensure that they match. The number of lines and pins used is minimized by multiplexing the EDC or ECC data with address signals and cycle type signals. The address and cycle type signals are placed on the time division multiplexed bidirectional lines at the beginning of a memory transfer cycle, and the EDC or ECC data is placed on these time division multiplexed lines at times when a longword of data is being transferred on a set of bidirectional data lines.