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29 条记录 (耗时 0.031 秒)

    Dual read/write register file memory
    24.
    发明授权
    Dual read/write register file memory 失效
    双读/写寄存器文件存储器

    公开(公告)号：US4933909A

    公开(公告)日：1990-06-12

    申请号：US286552

    申请日：1988-12-19

    申请人： David E. Cushing ,  Romeo Kharileh ,  Jian-Kuo Shen ,  Ming-Tzer Miu

    发明人： David E. Cushing ,  Romeo Kharileh ,  Jian-Kuo Shen ,  Ming-Tzer Miu

    IPC分类号： G11C11/41 ,  G06F12/00 ,  G11C8/16

    CPC分类号： G11C8/16

    摘要： A dual port read/write register file memory includes means for performing a read/modify write cycle of operation within a single system cycle of operation. The register file memory is constructed from one to more (RAM) addressable multibit storage arrays organized to form a dual read port, single write port RAM. Additionally, the register file includes a plurality of clocked input registers arranged in pairs for storing command, address and data signals for two write ports. The different pairs of registers are connected as inputs to a first set of multiplexer circuits whose outputs connect to the write control signal, address and data inputs of the single write port. The single write port of the register file memory is enabled for writing twice during each cycle. This allows data clocked into the input registers during the previous cycle to be written sequentially into the register file storage locations. By writing data into the input registers instead of the register file memory in a previous cycle, the time required for writing is reduced to a minimum.

    Resource conflict detection method and apparatus included in a pipelined processing unit
    28.
    发明授权
    Resource conflict detection method and apparatus included in a pipelined processing unit 失效
    资源冲突检测方法和装置包括在管道加工单元

    公开(公告)号：US5073855A

    公开(公告)日：1991-12-17

    申请号：US374882

    申请日：1989-06-30

    申请人： Deborah K. Staplin ,  Jian-Kuo Shen ,  Ming-Tzer Miu

    发明人： Deborah K. Staplin ,  Jian-Kuo Shen ,  Ming-Tzer Miu

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3838 ,  G06F9/3836

    摘要： A pipelined processing unit includes an instruction unit stage containing resource conflict apparatus for detecting and resolving conflicts in the use of register and indicator resources during the different phases of instruction execution. The instruction unit includes a plurality of resource registers corresponding in number to the number of instructions which can be processed concurrently by the processing unit. Decode circuits in response to each new instruction received by the instruction unit generate one or more sets of bit indication signals designating those resources required by the specific pipeline stage(s) executing the instruction for completing the execution of the instruction which are shared by those stages capable of completing the execution of instructions. Comparison circuits compare the set of bit indication signals for each new instruction that corresponds to resources needed by an earlier pipeline stage which in the preferred embodiment corresponds to a secondary execution unit, with the stored sets of bit indication signals for determining the presence of any resource conflict.

    Mechanism for automatically updating multiple unit register file memories in successive cycles for a pipelined processing system
    29.
    发明授权
    Mechanism for automatically updating multiple unit register file memories in successive cycles for a pipelined processing system 失效
    用于在流水线处理系统的连续循环中自动更新多个单元寄存器文件存储器的机构

    公开(公告)号：US4980819A

    公开(公告)日：1990-12-25

    申请号：US286551

    申请日：1988-12-19

    申请人： David E. Cushing ,  Richard P. Kelly ,  Robert V. Ledoux ,  Jian-Kuo Shen

    发明人： David E. Cushing ,  Richard P. Kelly ,  Robert V. Ledoux ,  Jian-Kuo Shen

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3834 ,  G06F9/3885

    摘要： A separate register file memory is included in at least two units of a pipelined processor which are located on separate integrated circuit chips. The register file memories of the units are interconnected so as to share certain input data register stages to enable updating to take place within a minimum of time. Each unit has a microprogrammed control unit which automatically provides update commands during the unit's cycles of operation. The signals from each microprogrammed control unit are applied to both register file memories enabling both memories to be updated during successive cycles of operation and thereby function collectively as one unit. This ensures that both units have access to the same most recently updated user visible information enabling both units to complete the execution of different instructions entering pipeline.

    摘要翻译： 位于分离的集成电路芯片上的流水线处理器的至少两个单元中包括单独的寄存器文件存储器。 这些单元的寄存器文件存储器被互连以便共享某些输入数据寄存器级，以使得能够在最短时间内进行更新。 每个单元都有一个微程序控制单元，在单元的操作周期内自动提供更新命令。 来自每个微程序控制单元的信号被应用于两个寄存器文件存储器，使得能够在连续的操作循环期间更新存储器，从而一起作为一个单元。 这样可以确保两个单元都可以访问同样最近更新的用户可见信息，使两个单元能够完成进入管道的不同指令的执行。