公开(公告)号：US5193181A

公开(公告)日：1993-03-09

申请号：US593458

申请日：1990-10-05

申请人： George J. Barlow ,  James W. Keeley ,  Richard A. Lemay ,  Jian-Kuo Shen ,  Robert V. Ledoux, deceased ,  Thomas F. Joyce ,  Richard P. Kelly ,  Robert C. Miller

发明人： George J. Barlow ,  James W. Keeley ,  Richard A. Lemay ,  Jian-Kuo Shen ,  Robert V. Ledoux, deceased ,  Thomas F. Joyce ,  Richard P. Kelly ,  Robert C. Miller

IPC分类号： G06F11/00 ,  G06F11/22

CPC分类号： G06F11/0793 ,  G06F11/0724 ,  G06F11/0766 ,  G06F11/004 ,  G06F11/2205

摘要： The pipelined central processing system (CSS) units of a multiprocessor system are tightly coupled to connect in common to a system bus for sharing main memory and input/output controllers/devices. The CSS includes several circuit boards for the different VLSI circuit chip pipelined stages and associated control circuits in addition to the bus interface unit (BIU) circuits. Each board includes one or more unusual event (UEV) detector circuits for signaling when the behavior of a stage is abnormal. The UEV fault signals from each board are collected by the BIU board. When a UEV fault is detected, the BIU board circuits prevent any further communications with the system bus and broadcasts the UEV fault signal to the other boards causing the different pipelined stages to emulate the completion of the instructions within the pipeline thereby flushing it. It is thereafter placed in a nonpipelined mode. Control circuits execute a UEV handler microcode routine which reads the contents of syndrome registers included on each board containing the UEV indicator states in addition to error signals into register file working locations. The UEV signal is then cleared enabling the BIU to resume communications with the sytem bus.

公开(公告)号：US5446847A

公开(公告)日：1995-08-29

申请号：US531

申请日：1993-01-04

申请人： James W. Keeley ,  George J. Barlow ,  Richard A. Lemay

发明人： James W. Keeley ,  George J. Barlow ,  Richard A. Lemay

IPC分类号： G06F13/372 ,  G06F13/18

CPC分类号： G06F13/372

摘要： A bus interface priority network provides access to a system bus by a plurality of different types of requestors as a function of the types of transactions they are required to process. The network includes programmable circuit for identifying the type of requestor and selecting a delay for accessing the system bus on the basis of requestor type thereby eliminating the need to adjust timing to the slowest requestor.

摘要翻译： 总线接口优先级网络通过多个不同类型的请求者提供对系统总线的访问，作为它们需要处理的事务的类型的函数。 该网络包括用于识别请求者的类型的可编程电路，并且基于请求者类型选择访问系统总线的延迟，从而消除了对最慢请求者调整定时的需要。

公开(公告)号：US5341495A

公开(公告)日：1994-08-23

申请号：US771297

申请日：1991-10-04

申请人： Thomas F. Joyce ,  James W. Keeley ,  Richard A. Lemay ,  Bruno DiPlacido, Jr. ,  Martin M. Massucci

发明人： Thomas F. Joyce ,  James W. Keeley ,  Richard A. Lemay ,  Bruno DiPlacido, Jr. ,  Martin M. Massucci

IPC分类号： G06F13/40 ,  G06F13/42 ,  G06F13/00 ,  G06F13/38

CPC分类号： G06F13/4027

摘要： A processing unit tightly couples to a system bus which utilizes a split cycle bus protocol and includes a local memory which is accessible from such bus. The local memory couples to a high speed synchronous bus which operates according to a predetermined bus protocol. The processing unit includes a state machine which couples to the high speed synchronous bus and to the asynchronous system bus. The state machine emulates the predetermined bus synchronous protocol in transferring commands issued to the local memory from the system bus which uses the split cycle protocol.

摘要翻译： 处理单元紧密地耦合到利用分离循环总线协议的系统总线，并且包括可以从这种总线访问的本地存储器。 本地存储器耦合到根据预定总线协议操作的高速同步总线。 处理单元包括耦合到高速同步总线和异步系统总线的状态机。 状态机在从使用分离周期协议的系统总线传送发给本地存储器的命令时模拟预定的总线同步协议。

公开(公告)号：US4764862A

公开(公告)日：1988-08-16

申请号：US717201

申请日：1985-03-28

申请人： George J. Barlow ,  James W. Keeley

发明人： George J. Barlow ,  James W. Keeley

IPC分类号： G06F11/00 ,  G06F13/42 ,  G06F13/14

CPC分类号： G06F13/4213 ,  G06F11/00

摘要： A data processing system includes a plurality of units which are coupled to transfer requests including data, command and integrity signals between units over a system bus during allocated bus transfer cycles. Each unit includes response apparatus for acknowledging requests received from other units. Each of a number of units further includes retry apparatus and like checking apparatus for verifying that the different parts of a request received from such unit over the bus are valid based upon the states of accompanying function identification signals. When less than all of the parts of the request defined as requiring verification are detected as valid, the receiving unit does not accept the request and inhibits its response apparatus from generating a response. This prevents damage to system integrity and permits each unit with retry apparatus to retry the request during a subsequent bus transfer cycle.

摘要翻译： 数据处理系统包括多个单元，其被耦合以在分配的总线传送周期期间通过系统总线在单元之间传送包括数据，命令和完整性信号的请求。 每个单元包括用于确认从其他单元接收的请求的响应装置。 多个单元中的每一个还包括重试设备和类似的检查装置，用于根据伴随的功能识别信号的状态来验证从该单元接收的请求的不同部分是否有效。 当被检测为需要验证的请求的全部部分被检测为有效时，接收单元不接受该请求并禁止其响应装置产生响应。 这样可以防止系统完整性受到损害，并允许每个重试设备的单元在随后的总线传输周期内重试该请求。

公开(公告)号：US4724519A

公开(公告)日：1988-02-09

申请号：US750117

申请日：1985-06-28

申请人： George J. Barlow ,  James W. Keeley ,  Elmer W. Carroll

发明人： George J. Barlow ,  James W. Keeley ,  Elmer W. Carroll

IPC分类号： G06F13/14 ,  G06F12/06 ,  G06F13/362 ,  G06F13/368 ,  G06F13/378 ,  G06F13/36

CPC分类号： G06F13/368 ,  G06F12/0623 ,  G06F13/378

摘要： A data processing system has a system bus network which includes a distributed priority network for transferring data asynchronously between a number of subsystems which couple to the bus. Each subsystem includes priority logic circuits coupled to receive a group of priority signals from the priority network which establish when the subsystem has the highest priority of the requesting subsystems to access the bus. The number of subsystems include a plurality of identical subsystems, each of which has a channel number assignment apparatus. The apparatus of each identical subsystem is connected to receive the same of at least one of the group of priority signals. During the idle state of the system bus, the apparatus of each identical subsystem operates to store a unique state of the priority signal which is defined as a function of the subsystem's position on the bus thereby automatically establishing a unique channel number value for each identical subsystem.

摘要翻译： 数据处理系统具有系统总线网络，该系统总线网络包括用于在耦合到总线的多个子系统之间异步地传送数据的分布式优先级网络。 每个子系统包括优先级逻辑电路，其被耦合以从优先级网络接收一组优先级信号，该优先级信号建立当子系统具有请求子系统访问总线的最高优先级时。 子系统的数量包括多个相同的子系统，每个子系统具有信道号分配装置。 每个相同子系统的装置被连接以接收该组优先级信号中的至少一个。 在系统总线的空闲状态期间，每个相同子系统的装置操作以存储优先级信号的唯一状态，其被定义为总线上子系统位置的函数，从而为每个相同的子系统自动建立唯一的信道数值 。

公开(公告)号：US5664200A

公开(公告)日：1997-09-02

申请号：US414983

申请日：1995-03-31

申请人： George J. Barlow ,  James W. Keeley

发明人： George J. Barlow ,  James W. Keeley

IPC分类号： G06F9/46 ,  G06F13/24 ,  G06F13/26 ,  G06F15/16 ,  G06F15/17 ,  G06F15/177 ,  G06F13/18

CPC分类号： G06F13/24 ,  G06F13/26 ,  G06F15/17

摘要： A multiprocessor computer system includes a number of processors, each processor having an interrupt mechanism and connecting in common to a system bus over which interrupt requests are communicated. When a processor accepts an interrupt request from another processor, it generates an acknowledge response on the system bus. If such processor contains a previous and pending interrupt request of an equal or higher priority level, it generates a not acknowledge response on the system bus and refuses the interrupt request. At the completion of servicing an interrupt request, each processor places on the system bus, an interrupt completed command including an address identifying such processor, a code designating a priority level to which it has switched and a code indicating that the processor has completing servicing an interrupt request. Each interrupt mechanism further includes interrupt retry means containing a refused interrupt register means for storing the channel address of the processor generating the not acknowledge in response and the priority level code contained in the interrupt request, and a level monitor logic unit connected to the system bus. The level monitor logic unit detects interrupt completed commands and compares the channel address and priority level code in the interrupt completed command to channel address and level code stored in the refused interrupt register means. When the processor channel addresses match and the level code is less than the level stored in the refused interrupt register means, the monitor logic unit generates a retry interrupt output. The processor retries the corresponding previously refused interrupt request upon receipt of the retry interrupt output.

摘要翻译： 多处理器计算机系统包括多个处理器，每个处理器具有中断机制并且共同连接到通过其传送中断请求的系统总线。 当处理器接受另一个处理器的中断请求时，它会在系统总线上产生一个确认响应。 如果这样的处理器包含等于或更高优先级的先前和未决的中断请求，它将在系统总线上产生不确认响应并拒绝中断请求。 在完成对中断请求的服务的完成时，每个处理器放置在系统总线上，一个中断完成命令，包括一个标识这样的处理器的地址，一个指定其所切换的优先级的代码，以及一个指示处理器完成服务的代码 中断请求。 每个中断机制还包括中断重试装置，其中包含一个拒绝中断寄存器装置，用于存储响应中产生不应答的处理器的通道地址以及中断请求中包含的优先级代码，以及连接到系统总线的电平监视逻辑单元 。 电平监视逻辑单元检测中断完成命令，并将中断完成命令中的通道地址和优先级代码与存储在拒绝中断寄存器装置中的通道地址和电平代码进行比较。 当处理器通道地址匹配并且电平代码小于存储在拒绝中断寄存器装置中的电平时，监视器逻辑单元产生重试中断输出。 接收到重试中断输出后，处理器重试相应的先前拒绝的中断请求。

公开(公告)号：US4839800A

公开(公告)日：1989-06-13

申请号：US901847

申请日：1986-08-29

申请人： George J. Barlow ,  James W. Keeley

发明人： George J. Barlow ,  James W. Keeley

IPC分类号： G06F13/26

CPC分类号： G06F13/26

摘要： A multiprocessor system includes a number of subsystems all coupled in common to an asynchronous system bus. Apparatus is included in the system bus interface logic of each processing subsystem to receive commands from the system bus and compare the interrupt priority level of the new command with the current command being executed. If the new command has a lower interrupt priority than the current command, then the subsystem sending the command will receive a not acknowledge response from the processing system. The apparatus is responsive to certain control signals from the new command to bypass the interrupt priority comparison logic and initiate an immediate interrupt regardless of the interrupt priority level of the current command being executed by the processing subsystem. The processing subsystem may also generate a command to itself via the system bus which requires the high speed interrupt.

摘要翻译： 多处理器系统包括多个子系统，所有子系统共同连接到异步系统总线。 装置包括在每个处理子系统的系统总线接口逻辑中，以从系统总线接收命令，并将新命令的中断优先级与正在执行的当前命令进行比较。 如果新命令的中断优先级低于当前命令，则发送命令的子系统将从处理系统接收到未确认的响应。 该装置响应于来自新命令的某些控制信号绕过中断优先级比较逻辑并且启动立即中断，而不管处理子系统正在执行的当前命令的中断优先级。 处理子系统还可以经由需要高速中断的系统总线对其自身产生命令。

公开(公告)号：US5367697A

公开(公告)日：1994-11-22

申请号：US781513

申请日：1991-10-22

申请人： George J. Barlow ,  James W. Keeley

发明人： George J. Barlow ,  James W. Keeley

IPC分类号： G06F11/00 ,  G06F1/30

CPC分类号： G06F11/1441

摘要： A multiprocessor computer system includes first processors, second processors, a system management means for performing system management functions, including detecting pending power shut-downs and sending power shut-down messages addressed to each of the first processors warning of pending power shut-downs, and a system bus for communication between the first and second processors and the system management means, including the communication of pending power shut-down messages. The first processors include interrupt handling means responsive to pending power shut-down messages for executing power shut-down routines for placing the first processors into a known state before power termination, but the second processors inherently do not include a power shut-down capability. In each of the second processors, a power shut-down means is provided to place the second processors in a known state before a power termination, including a bus monitor connected from the system bus and responsive to any power shut-down message addressed to a first processor for generating an output indicating the occurrence of a power shut-down message to a first processor. The second processor also includes non-maskable interrupt logic connected from the power shut-down message output of the bus monitor and responsive to the power shut-down message output of the bus monitor for generating a non-maskable interrupt output to the second processor. The second processor is in turn responsive to a non-maskable interrupt output of the non-maskable logic for querying the non-maskable logic to determine the nature of the interrupt, and responsive to the indicated occurrence of a power shut-down message to any first processor for executing a power shut-down routine for placing the second processor in a known state before the termination of power.

摘要翻译： 多处理器计算机系统包括第一处理器，第二处理器，用于执行系统管理功能的系统管理装置，包括检测待处理的电源关闭，以及发送寻址到每个第一处理器的停电功率停止消息， 以及用于在第一和第二处理器与系统管理装置之间进行通信的系统总线，包括待处理的电力关闭消息的通信。 第一处理器包括响应于等待的电源关闭消息的中断处理装置，用于执行电源关闭例程，以在电源终止之前将第一处理器置于已知状态，但是第二处理器固有地不包括电源关闭功能。 在每个第二处理器中，提供电源关闭装置以在电源终止之前将第二处理器置于已知状态，包括从系统总线连接的总线监视器，并且响应于任何电源关闭消息 第一处理器，用于产生指示向第一处理器发出电力关闭消息的输出。 第二处理器还包括从总线监视器的电源关闭消息输出连接的不可屏蔽中断逻辑，并且响应于总线监视器的电源关闭消息输出，以产生对第二处理器的不可屏蔽中断输出。 第二处理器又响应于不可屏蔽逻辑的不可屏蔽中断输出，用于查询不可屏蔽逻辑以确定中断的性质，并且响应于所指示的电力关闭消息发生到任何 第一处理器，用于在电源结束之前执行用于将第二处理器置于已知状态的电源关闭程序。

公开(公告)号：US4833601A

公开(公告)日：1989-05-23

申请号：US55577

申请日：1987-05-28

申请人： George J. Barlow ,  James W. Keeley ,  Chester M. Nibby, Jr.

发明人： George J. Barlow ,  James W. Keeley ,  Chester M. Nibby, Jr.

IPC分类号： G06F11/00 ,  G06F11/07 ,  G06F11/14 ,  G06F11/16 ,  G06F12/08 ,  G06F12/10

CPC分类号： G06F11/073 ,  G06F11/0724 ,  G06F11/0793 ,  G06F12/0815 ,  G06F11/0757 ,  G06F11/141

摘要： A cache memory subsystem has multilevel directory memory and buffer memory pipeline stages shared by at least a pair of independently operated central processing units and a first in first out (FIFO) device which connects to a system bus of a tightly coupled data processing system. The cache subsystem includes a number of programmable control circuits which are connected to receive signals representative of the type of operations performable by the cache subsystem. These signals are logically combined for generating an output signal indicating whether or not the contents of the directiory memory should be flushed when any one of a number of types of address or system faults has been detected in order to maintain cache coherency.

公开(公告)号：US4763243A

公开(公告)日：1988-08-09

申请号：US623264

申请日：1984-06-21

申请人： George J. Barlow ,  James W. Keeley

发明人： George J. Barlow ,  James W. Keeley

IPC分类号： G06F11/00 ,  G06F13/42 ,  G06F13/14 ,  G06F13/38

CPC分类号： G06F13/4213 ,  G06F11/00

摘要： A data processing system includes a plurality of units which are coupled to transfer requests including data, command and integrity signals between units over a system bus during allocated bus transfer cycles. Each unit includes response apparatus for acknowledging requests received from other units. Each of a number of units further includes retry apparatus and checking apparatus for verifying that all of the parts of a request received from such unit over the bus are valid. When less than all of the parts of the request are detected as valid, the receiving unit does not accept the request and inhibits its response apparatus from generating a response. This prevents damage to system integrity and permits each unit with retry apparatus to retry the request during a subsequent bus transfer cycle.

摘要翻译： 数据处理系统包括多个单元，其被耦合以在分配的总线传送周期期间通过系统总线在单元之间传送包括数据，命令和完整性信号的请求。 每个单元包括用于确认从其他单元接收的请求的响应装置。 多个单元中的每一个还包括重试设备和检查装置，用于验证从总线上接收到的单元的所有请求的所有部分都是有效的。 当小于所有请求的部分被检测为有效时，接收单元不接受该请求并且禁止其响应装置产生响应。 这样可以防止系统完整性受到损害，并允许每个重试设备的单元在随后的总线传输周期内重试该请求。