公开(公告)号：US5193181A

公开(公告)日：1993-03-09

申请号：US593458

申请日：1990-10-05

申请人： George J. Barlow ,  James W. Keeley ,  Richard A. Lemay ,  Jian-Kuo Shen ,  Robert V. Ledoux, deceased ,  Thomas F. Joyce ,  Richard P. Kelly ,  Robert C. Miller

发明人： George J. Barlow ,  James W. Keeley ,  Richard A. Lemay ,  Jian-Kuo Shen ,  Robert V. Ledoux, deceased ,  Thomas F. Joyce ,  Richard P. Kelly ,  Robert C. Miller

IPC分类号： G06F11/00 ,  G06F11/22

CPC分类号： G06F11/0793 ,  G06F11/0724 ,  G06F11/0766 ,  G06F11/004 ,  G06F11/2205

摘要： The pipelined central processing system (CSS) units of a multiprocessor system are tightly coupled to connect in common to a system bus for sharing main memory and input/output controllers/devices. The CSS includes several circuit boards for the different VLSI circuit chip pipelined stages and associated control circuits in addition to the bus interface unit (BIU) circuits. Each board includes one or more unusual event (UEV) detector circuits for signaling when the behavior of a stage is abnormal. The UEV fault signals from each board are collected by the BIU board. When a UEV fault is detected, the BIU board circuits prevent any further communications with the system bus and broadcasts the UEV fault signal to the other boards causing the different pipelined stages to emulate the completion of the instructions within the pipeline thereby flushing it. It is thereafter placed in a nonpipelined mode. Control circuits execute a UEV handler microcode routine which reads the contents of syndrome registers included on each board containing the UEV indicator states in addition to error signals into register file working locations. The UEV signal is then cleared enabling the BIU to resume communications with the sytem bus.

公开(公告)号：US4321665A

公开(公告)日：1982-03-23

申请号：US8121

申请日：1979-01-31

申请人： Jian-Kuo Shen ,  John J. Bradley ,  Richard L. King ,  Robert C. Miller ,  Ming T. Miu ,  Theodore R. Staplin, Jr.

发明人： Jian-Kuo Shen ,  John J. Bradley ,  Richard L. King ,  Robert C. Miller ,  Ming T. Miu ,  Theodore R. Staplin, Jr.

IPC分类号： G06F13/40 ,  G06F3/00

CPC分类号： G06F13/4013

摘要： In a data processing system which includes a central processing unit (CPU), main memory and a plurality of input/output controllers (IOCs) connected to a common bus information can be transferred between the main memory and CPU and main memory and the IOCs. Logic is provided within the CPU to align a byte of data on the data lines of the common bus such that it can be taken from the data lines by the main memory and written into a multi byte word without further alignment. Logic is provided within the CPU to extract from a multi byte word of data read from main memory and appearing on the common bus data lines the appropriate byte of data and to align it on the common bus data lines such that an IOC may pass the data byte to a peripheral device without further alignment.

摘要翻译： 在包括中央处理单元（CPU）的数据处理系统中，主存储器和连接到公共总线信息的多个输入/输出控制器（IOC）可以在主存储器和CPU以及主存储器和IOC之间传送。 在CPU内部提供逻辑，以便在公共总线的数据线上对齐一个数据字节，使得它可以从主存储器从数据线中取出，并写入多字节字而无需进一步对齐。 在CPU中提供逻辑以从从主存储器读取的数据的多字节字提取出公共总线数据线上相应的数据字节并将其对准在公共总线数据线上，使得IOC可以传递数据 字节到外围设备，无需进一步对齐。

公开(公告)号：US4383295A

公开(公告)日：1983-05-10

申请号：US11001

申请日：1979-02-09

申请人： Robert C. Miller ,  John J. Bradley ,  Boyd E. Darden ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

发明人： Robert C. Miller ,  John J. Bradley ,  Boyd E. Darden ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

IPC分类号： G06F3/02 ,  G06F9/06

CPC分类号： G06F3/0227

摘要： In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processor unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and later provides the CPU with a channel number assigned to the requesting IOC. In order to allow a data entry operator inputting data via a peripheral device connected to an IOC the ability to correct errors, a backspace character is provided so that the operator can enter it to indicate to the system to ignore the preceding character. Logic is provided within the system to allow a DMC IOC to detect the output of a backspace character from the peripheral device connected to the IOC and to inform the CPU of the entry of the backspace character by a special (backspace) input/output interrupt. Further logic is provided within the CPU to adjust pointers to the main memory input buffer to effectively ignore the byte of data corresponding to the character preceding the backspace character. Still further logic is provided within the DMC IOC to prohibit the sending of special (backspace) input/output interrupts to the CPU if there are no bytes of data remaining in the input buffer.

摘要翻译： 在包括一个或多个公共总线的数据处理系统中，多个输入/输出控制器连接到该公共总线用于传送数据，数据块可以在主存储器和与操作同步的输入/输出控制器（IOC）之间传送 的中央处理器单元（CPU）。 提供逻辑用于在数据复用控制（DMC）数据传输操作期间传输一个数据单元，其中请求的IOC请求CPU的DMC数据传输，并且稍后向CPU提供分配给请求的IOC的通道号 。 为了允许数据输入操作者通过连接到IOC的外围设备输入数据以校正错误的能力，提供退格字符，以便操作者可以进入它以指示系统忽略前一个字符。 在系统中提供逻辑，以允许DMC IOC从连接到IOC的外围设备检测退格字符的输出，并通过特殊（退格）输入/输出中断向CPU通知退格字符的输入。 在CPU内提供进一步的逻辑来调整指向主存储器输入缓冲器的指针，以有效地忽略与退格字符之前的字符相对应的数据字节。 在DMC IOC中还提供了一些逻辑，以禁止在CPU中输入/输出特殊的（空格）输入/输出中断，如果输入缓冲区中没有字节数据。

公开(公告)号：US4300193A

公开(公告)日：1981-11-10

申请号：US8003

申请日：1979-01-31

申请人： John J. Bradley ,  Robert C. Miller ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

发明人： John J. Bradley ,  Robert C. Miller ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

IPC分类号： G06F13/28 ,  G06F3/00

CPC分类号： G06F13/282

摘要： In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of information, blocks of information may be transferred between main memory and an input/output controller (IOC) synchronously with operations of the central processor unit (CPU). Logic is provided for enabling one unit of the block of information to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and provides the CPU with a channel number assigned to the requesting IOC. Means are provided within the CPU for determining: the direction of the data transfer, the address of the location of the unit of data to be transferred to/from the main memory, and the number of units of data remaining to be transferred between the main memory and the IOC.

摘要翻译： 在包括一个或多个公共总线的数据处理系统中，多个输入/输出控制器连接到多个输入/输出控制器用于信息的传送，信息块可以在主存储器和与操作同步的输入/输出控制器（IOC）之间传送 的中央处理器单元（CPU）。 逻辑被提供用于使得在数据复用控制（DMC）数据传送操作期间传送信息块的一个单元，其中请求的IOC请求CPU的DMC数据传送，并向CPU提供分配给 请求IOC。 在CPU内提供用于确定：数据传送的方向，要传送到主存储器的数据单元的位置的地址以及在主存储器之间传输的剩余数据的单元数量 记忆和国际奥委会。

公开(公告)号：US4495571A

公开(公告)日：1985-01-22

申请号：US339278

申请日：1982-01-15

申请人： Theodore R. Staplin, Jr. ,  John J. Bradley ,  Richard L. King ,  Robert C. Miller ,  Ming T. Miu ,  Jian-Kuo Shen

发明人： Theodore R. Staplin, Jr. ,  John J. Bradley ,  Richard L. King ,  Robert C. Miller ,  Ming T. Miu ,  Jian-Kuo Shen

IPC分类号： G06F13/12 ,  G06F13/362 ,  G06F3/04 ,  G06F13/00

CPC分类号： G06F13/122 ,  G06F13/362

摘要： A data processing system which includes a central processing unit coupled over a common bus with a plurality of input/output controllers (IOCs) and main memory includes apparatus which allows an IOC to signal the CPU to wait and retry the current I/O instruction. Other apparatus is provided which enables the CPU to continually retry the I/O instruction until the IOC accepts or rejects the I/O instruction and which further allows the CPU to suspend the retrying of the I/O instruction and to process interrupt requests and data transfer requests from any one of the plurality of IOCs. After processing the interrupt or data transfer request, system control is returned to retrying the I/O instruction.

摘要翻译： 包括通过公共总线与多个输入/输出控制器（IOC）和主存储器耦合的中央处理单元的数据处理系统包括允许IOC发信号通知CPU等待并重试当前I / O指令的装置。 提供了其他设备，使得CPU能够连续地重试I / O指令，直到IOC接受或拒绝I / O指令，并且还允许CPU暂停重试I / O指令并处理中断请求和数据 转移来自多个IOC中的任何一个的请求。 处理中断或数据传输请求后，返回系统控制以重试I / O指令。

公开(公告)号：US4292668A

公开(公告)日：1981-09-29

申请号：US8002

申请日：1979-01-31

申请人： Robert C. Miller ,  John J. Bradley ,  Richard L. King ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

发明人： Robert C. Miller ,  John J. Bradley ,  Richard L. King ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

IPC分类号： G06F13/28 ,  G06F13/362 ,  G06F3/00

CPC分类号： G06F13/362 ,  G06F13/285

摘要： In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processor unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Data Multiplex Control (DMC) data transfer operation in which the requesting IOC requests a DMC data transfer of the CPU and later provides the CPU with a channel number assigned to the requesting IOC. Means are provided within the system for: resolvng conflicting requests for the one or more common buses, the CPU to acknowledge the DMC request, identifying the requesting IOC to the CPU, accessing one unit of data from main memory or the IOC, and transferring the unit of data to the IOC or main memory.

摘要翻译： 在包括一个或多个公共总线的数据处理系统中，多个输入/输出控制器连接到该公共总线用于传送数据，数据块可以在主存储器和与操作同步的输入/输出控制器（IOC）之间传送 的中央处理器单元（CPU）。 提供逻辑用于在数据复用控制（DMC）数据传输操作期间传输一个数据单元，其中请求的IOC请求CPU的DMC数据传输，并且稍后向CPU提供分配给请求的IOC的通道号 。 在系统内提供了：解决对一个或多个公共总线的冲突请求，CPU确认DMC请求，识别请求的IOC到CPU，从主存储器或IOC访问一个单元的数据，并传送 数据单位到IOC或主存储器。

公开(公告)号：US4293908A

公开(公告)日：1981-10-06

申请号：US8001

申请日：1979-01-31

申请人： John J. Bradley ,  Thomas O. Holtey ,  Robert C. Miller ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

发明人： John J. Bradley ,  Thomas O. Holtey ,  Robert C. Miller ,  Ming T. Miu ,  Jian-Kuo Shen ,  Theodore R. Staplin, Jr.

IPC分类号： G06F13/28 ,  G06F13/362 ,  G06F13/00

CPC分类号： G06F13/362 ,  G06F13/282

摘要： In a data processing system which includes one or more common buses to which a plurality of input/output controllers are connected for the transfer of data, blocks of data may be transferred between main memory and an input/output controller (IOC) synchronously with operation of the central processing unit (CPU). Logic is provided for enabling one unit of data to be transferred during a Direct Memory Access (DMA) data transfer operation in which the requesting IOC requests a DMA data transfer of the CPU. Means are provided within the system for: resolving conflicting requests for the one or more common buses, the CPU to acknowledge the DMA request, the IOC to transfer the address of the location where the unit of data is to be written into main memory followed by the unit of data, or the IOC to transfer the address of the location in main memory from which the unit of data is to be read and then receive the unit of data read from main memory.

摘要翻译： 在包括一个或多个公共总线的数据处理系统中，多个输入/输出控制器连接到该公共总线用于传送数据，数据块可以在主存储器和与操作同步的输入/输出控制器（IOC）之间传送 的中央处理单元（CPU）。 提供逻辑用于在直接存储器访问（DMA）数据传输操作期间传送一个数据单元，其中请求IOC请求CPU的DMA数据传输。 在系统内提供的装置是：解决对一个或多个公共总线的冲突请求，CPU确认DMA请求，IOC将要写入数据单元的位置的地址传送到主存储器，之后是 数据单元或IOC传输要从其读取数据单元的主存储器中的位置的地址，然后接收从主存储器读取的数据单元。

公开(公告)号：US4727486A

公开(公告)日：1988-02-23

申请号：US858786

申请日：1986-05-02

申请人： Michael D. Smith ,  Llewelyn S. Dunwell ,  Richard A. Lemay ,  Robert C. Miller ,  Theodore R. Staplin, Jr. ,  William E. Woods ,  John L. Curley

发明人： Michael D. Smith ,  Llewelyn S. Dunwell ,  Richard A. Lemay ,  Robert C. Miller ,  Theodore R. Staplin, Jr. ,  William E. Woods ,  John L. Curley

IPC分类号： G06F12/10 ,  G06F9/00 ,  G06F9/22 ,  G06F9/30

CPC分类号： G06F12/1054

摘要： A data processing system includes a central processor unit (CPU), a main memory and a memory management unit (MMU). Information is stored in main memory in segments, each segment being identified by a segment descriptor stored in a translation table in the MMU. Logical addresses from the CPU address segment descriptors in the MMU's translation table. These segment descriptors include the physical address of the location in main memory of the first word of the segment. If the segment descriptor is not in the translation table location, then the MMU operation is suspended while the segment descriptor is demand fetched from main memory.

公开(公告)号：US5148533A

公开(公告)日：1992-09-15

申请号：US294534

申请日：1989-01-05

申请人： Thomas F. Joyce ,  Robert C. Miller ,  Marc C. Vogt

发明人： Thomas F. Joyce ,  Robert C. Miller ,  Marc C. Vogt

IPC分类号： G06F12/08

CPC分类号： G06F12/0831

摘要： In a data processing system having a plurality of tightly coupled data processing units connected by an asynchronous system bus, apparatus and an associated method are described for maintaining the coherency of data groups stored in instruction cache units and execution cache units. The apparatus includes a monitor unit as part of the bus interface unit, and a bus interface unit coupling each associated data processing unit to the system bus. The monitor unit receives signals, applied to the system bus, identifying data groups transferred between the memory unit and the data processing units, including those data groups originating from the bus interface unit of which the monitor unit is a component. The bus interface unit includes directories duplicating the contents of the instruction cache unit directory and the execution cache unit directory. The monitor unit, in response to signals applied to the system bus, identifies operations that can compromise the integrity of signals stored in the associated data processing unit. The monitor unit accesses the appropriate duplicate directory to determine if the address of a compromised data group validly exists in the duplicate directory. When an address is stored in the duplicate directory along with a valid signal, the valid signal is removed from both the cache directory and the duplicate directory.

摘要翻译： 在具有通过异步系统总线连接的多个紧密耦合的数据处理单元的数据处理系统中，描述了用于维持存储在指令高速缓存单元和执行高速缓存单元中的数据组的一致性的装置和相关联的方法。 该装置包括作为总线接口单元的一部分的监视器单元和将每个相关联的数据处理单元耦合到系统总线的总线接口单元。 监视器单元接收施加到系统总线的信号，识别在存储器单元和数据处理单元之间传送的数据组，包括源自监视器单元是组件的总线接口单元的那些数据组。 总线接口单元包括复制指令高速缓存单元目录和执行高速缓存单元目录的内容的目录。 监视器单元响应于施加到系统总线的信号来识别可能危及存储在相关联的数据处理单元中的信号的完整性的操作。 监视器单元访问适当的重复目录，以确定受损数据组的地址是否有效存在于重复目录中。 当地址与有效信号一起存储在重复目录中时，有效信号将从缓存目录和重复目录中移除。

公开(公告)号：US08852999B2

公开(公告)日：2014-10-07

申请号：US13235852

申请日：2011-09-19

申请人： Hem Takiar ,  Robert C. Miller ,  Warren Middlekauff ,  Michael W. Patterson ,  Shrikar Bhagath

发明人： Hem Takiar ,  Robert C. Miller ,  Warren Middlekauff ,  Michael W. Patterson ,  Shrikar Bhagath

IPC分类号： H01L21/00 ,  H01L33/00 ,  G06K19/077 ,  H01L25/16 ,  H01L21/56 ,  H01L25/065 ,  G11C5/04 ,  H01L23/31 ,  H01L31/0203 ,  H01L23/29 ,  H01L23/28 ,  H01L21/50 ,  H01L23/00 ,  H05K3/00 ,  H05K1/18

CPC分类号： G06K19/07745 ,  G06K19/07732 ,  G11C5/04 ,  H01L21/565 ,  H01L23/3107 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/16 ,  H01L2223/5442 ,  H01L2223/54433 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/32145 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/181 ,  H05K3/0052 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： A system-in-a-package based flash memory card including an integrated circuit package occupying a small overall area within the card and cut to conform to the shape of a lid for the card. An integrated circuit may be cut from a panel into a shape that fits within and conforms to the shape of lids for a finished memory card, such as for example an SD Card. The integrated circuit package may be a system-in-a-package, a multi-chip module, or other arrangement where a complete electronic system is formed in a single package.

摘要翻译： 一种基于系统的基于包的闪存卡，其包括集成电路封装，其占据卡内的小的整体区域并且被切割以符合卡的盖的形状。 集成电路可以从面板切割成适合于并符合成品存储卡（例如SD卡）的盖的形状的形状。 集成电路封装可以是系统级封装，多芯片模块或其中在单个封装中形成完整电子系统的其它布置。