公开(公告)号：US11054461B1

公开(公告)日：2021-07-06

申请号：US16351310

申请日：2019-03-12

Applicant: Xilinx, Inc.

Inventor： Nui Chong ,  Amitava Majumdar ,  Cheang-Whang Chang ,  Henley Liu ,  Myongseob Kim ,  Albert Shih-Huai Lin

IPC: G01R31/28 ,  G01R31/3185 ,  G01R31/3177 ,  H01L25/065

Abstract: Device(s) and method(s) related generally to a wafer or die stack are disclosed. In one such device, a die stack of two or more integrated circuit dies has associated therewith test circuits corresponding to each level of the die stack each with a set of pads. A test data-input path includes being from: a test data-in pad through a test circuit to a test data-out pad of each of the test circuits; and the test data-out pad to the test data-in pad between consecutive levels of the test circuits. Each of the set of pads includes the test data-in pad and the test data-out pad respectively thereof. A test data-output path is coupled to the test data-out pad of a level of the levels.

公开(公告)号：US10756711B1

公开(公告)日：2020-08-25

申请号：US16682835

申请日：2019-11-13

Applicant: XILINX, INC.

Inventor： Amitava Majumdar ,  Nui Chong

IPC: H03K3/03 ,  H03K3/017 ,  H03K3/011

Abstract: Examples described herein provide determining skew of transistors on an integrated circuit. In an example, an integrated circuit includes a ring oscillator and first and second detector circuits. The ring oscillator includes serially connected buffers. Each buffer includes serially connected inverters that include transistors. A transistor of each buffer has a different strength of another transistor of the respective buffer. The first and second detector circuits are connected to different first and second tap nodes, respectively, along the serially connected buffers. The first detector circuit is configured to count a number of cycles of a reference clock that a cyclic signal on the first tap node is either a logically high or low level. The second detector circuit is configured to count a number of cycles of the reference clock that a cyclic signal on the second tap node is either a logically high or low level.

公开(公告)号：US09865567B1

公开(公告)日：2018-01-09

申请号：US15423303

申请日：2017-02-02

Applicant: Xilinx, Inc.

Inventor： Raghunandan Chaware ,  Ganesh Hariharan ,  Inderjit Singh ,  Amitava Majumdar ,  Glenn O'Rourke

IPC: H01L21/58 ,  H01L25/065 ,  H01L25/00 ,  H01L21/82 ,  H01L21/66 ,  H01L23/00 ,  H01L21/56 ,  H01L25/16

CPC classification number: H01L25/0655 ,  H01L21/563 ,  H01L21/82 ,  H01L22/14 ,  H01L22/20 ,  H01L24/17 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/17181

Abstract: An example method of manufacturing a semiconductor assembly includes: forming first integrated circuit (IC) dies and dummy dies; forming an interposer wafer including a top side having first mounting sites for the first IC dies and second mounting sites for second IC dies; attaching the first IC dies to the interposer wafer at the first mounting sites and the dummy dies to the interposer wafer at the second mounting sites; processing a backside and the top side of the interposer wafer; removing the dummy dies from the top side of the interposer wafer to expose the second mounting sites; and attaching the second IC dies to the interposer wafer at the exposed second mounting sites.