公开(公告)号：US08853666B2

公开(公告)日：2014-10-07

申请号：US12159599

申请日：2006-10-25

申请人： Takashi Inoue ,  Tatsuo Nakayama ,  Yuji Ando ,  Yasuhiro Murase ,  Kazuki Ota ,  Hironobu Miyamoto ,  Katsumi Yamanoguchi ,  Naotaka Kuroda ,  Akio Wakejima ,  Yasuhiro Okamoto

发明人： Takashi Inoue ,  Tatsuo Nakayama ,  Yuji Ando ,  Yasuhiro Murase ,  Kazuki Ota ,  Hironobu Miyamoto ,  Katsumi Yamanoguchi ,  Naotaka Kuroda ,  Akio Wakejima ,  Yasuhiro Okamoto

IPC分类号： H01L29/06 ,  H01L29/15 ,  H01L29/778 ,  H01L29/423 ,  H01L29/20

CPC分类号： H01L29/7783 ,  H01L29/0607 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/7787

摘要： In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer). To gate length Lg of a FET to be prepared, a sum a of layer thicknesses of an electron supply layer and a channel layer is selected so as to fulfill Lg/a≧5, and in such a case, the layer thickness of the channel layer is selected in a range of not exceeding 5 times (about 500 Å) as long as a de Broglie wavelength of two-dimensional electron gas accumulated in the channel layer in room temperature.

摘要翻译： 在III族氮化物型场效应晶体管中，本发明通过缓冲层中的残留载流子的传导来减少漏电流成分，并且可以实现击穿电压的提高，并提高载流子限制效应（载流子限制） 提高夹断特性的通道（抑制短路效应）。 例如，当将本发明应用于GaN型场效应晶体管时，除了沟道层的GaN之外，使用其中铝组成逐渐或逐步朝向顶部的组分调制（组成梯度）AlGaN层用作 缓冲层（杂质缓冲液）。 对于要制备的FET的栅极长度Lg，选择电子供给层和沟道层的层厚度的和a以满足Lg /a≥5，并且在这种情况下，沟道的层厚度 只要在室温下积聚在通道层中的二维电子气的德布罗意波长，不超过5倍（约500）的范围内选择层。

公开(公告)号：US08466495B2

公开(公告)日：2013-06-18

申请号：US13468373

申请日：2012-05-10

申请人： Yuji Ando ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Yasuhiro Murase ,  Kazuki Ota ,  Akio Wakejima ,  Naotaka Kuroda

发明人： Yuji Ando ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Yasuhiro Murase ,  Kazuki Ota ,  Akio Wakejima ,  Naotaka Kuroda

IPC分类号： H01L29/80

CPC分类号： H01L29/7787 ,  H01L29/2003

摘要： Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0≦y≦1); a carrier supply layer 13 composed of AlxGa1-xN (0≦x≦1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x

摘要翻译： 公开了一种HJFET 110，其包括：由In y Ga 1-y N（0 @ y 1）组成的沟道层12; 由Al x Ga 1-x N（0 @ x 1）构成的载流子供给层13，载流子供给层13设置在沟道层12上并且包括至少一个p型层; 以及源极电极15S，漏极电极15D和栅极电极17，其通过p型层面对沟道层12，并且设置在载流子供给层13上。满足以下关系式：5.6×10×11× NA×eta×t [cm-2] <5.6×1013x，其中x表示载体供给层的Al组成比，t表示所述p型层的厚度，NA表示杂质浓度，eta表示活化 比。

公开(公告)号：US08426895B2

公开(公告)日：2013-04-23

申请号：US12735817

申请日：2009-03-23

申请人： Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yuji Ando

发明人： Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yuji Ando

IPC分类号： H01L29/205

CPC分类号： H01L29/7813 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/66734

摘要： A semiconductor device capable of suppressing the occurrence of a punch-through phenomenon is provided. A first n-type conductive layer (2′) is formed on a substrate (1′). A p-type conductive layer (3′) is formed thereon. A second n-type conductive layer (4′) is formed thereon. On the under surface of the substrate (1′), there is a drain electrode (13′) connected to the first n-type conductive layer (2′). On the upper surface of the substrate (1′), there is a source electrode (11′) in ohmic contact with the second n-type conductive layer (4′), and a gate electrode (12′) in contact with the first n-type conductive layer (2′), p-type conductive layer (3′), the second n-type conductive layer (4′) through an insulation film (21′). The gate electrode (12′) and the source electrode (11′) are alternately arranged. The p-type conductive layer (3′) includes In.

摘要翻译： 提供能够抑制穿通现象发生的半导体器件。 在基板（1'）上形成第一n型导电层（2'）。 在其上形成p型导电层（3'）。 在其上形成第二n型导电层（4'）。 在基板（1'）的下表面上，连接有第一n型导电层（2'）的漏电极（13'）。 在基板（1'）的上表面上存在与第二n型导电层（4'）欧姆接触的源电极（11'）和与第一n型导电层（4'）接触的栅电极（12'） n型导电层（2'），p型导电层（3'），通过绝缘膜（21'）的第二n型导电层（4'）。 栅电极（12'）和源电极（11'）交替排列。 p型导电层（3'）包括In。

公开(公告)号：US08344422B2

公开(公告)日：2013-01-01

申请号：US12810096

申请日：2008-12-25

申请人： Yuji Ando ,  Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Tatsuo Nakayama ,  Hironobu Miyamoto

发明人： Yuji Ando ,  Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Tatsuo Nakayama ,  Hironobu Miyamoto

IPC分类号： H01L29/66 ,  H01L29/08 ,  H01L29/778

CPC分类号： H01L29/66462 ,  H01L27/0605 ,  H01L29/0891 ,  H01L29/2003 ,  H01L29/4232 ,  H01L29/7781

摘要： A semiconductor device includes a lower barrier layer 12 composed of a layer of AlxGa1-xN (0≦x≦1) in a state of strain relaxation, and a channel layer 13, which is composed of a layer of InyGa1-yN (0≦y≦1) disposed on the lower barrier layer 12, has band gap that is smaller than band gap of the lower barrier layer 12, and exhibits compressive strain. A gate electrode 1G is formed over the channel layer 13 via an insulating film 15 and a source electrode 1S and a drain electrode 1D serving as ohmic electrodes are formed over the channel layer 13. The insulating film 15 is constituted of polycrystalline or amorphous member.

摘要翻译： 半导体器件包括在应变松弛的状态下由Al x Ga 1-x N（0＆amp; nlE; x＆nlE; 1）层构成的下阻挡层12，以及由In y Ga 1-y N（0＆lt; nlE; 1）层组成的沟道层13。 y）; 1）设置在下阻挡层12上，具有小于下阻挡层12的带隙的带隙，并且表现出压缩应变。 在沟道层13上经由绝缘膜15形成栅极电极1G，在沟道层13上形成有用作欧姆电极的源电极1S和漏电极1D。绝缘膜15由多晶或非晶构成。

公开(公告)号：US20120228674A1

公开(公告)日：2012-09-13

申请号：US13497557

申请日：2010-06-16

申请人： Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yuji Ando

发明人： Yasuhiro Okamoto ,  Kazuki Ota ,  Takashi Inoue ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yuji Ando

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/1054 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/267 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66734

摘要： Provided is a semiconductor device capable of suppressing an occurrence of a punch-through phenomenon.A semiconductor device includes a substrate 1, a first n-type semiconductor layer 2, a p-type semiconductor layer 3, a second n-type semiconductor layer 4, a drain electrode 13, a source electrode 11, a gate electrode 12, and a gate insulation film 21, wherein the first n-type semiconductor layer 2, the p-type semiconductor layer 3, and the second n-type semiconductor layer 4 are laminated on the substrate 1 in this order. The drain electrode 13 is in ohmic-contact with the first n-type semiconductor layer 2. The source electrode 11 is in ohmic-contact with the second n-type semiconductor layer 4. An opening portion to be filled or a notched portion that extends from an upper surface of the second n-type semiconductor layer 4 to an upper part of the first n-type semiconductor layer 2 is formed at a part of the p-type semiconductor layer 3 and a part of the second n-type semiconductor layer 4. The gate electrode 12 is in contact with an upper surface of the first n-type semiconductor layer 2, side surfaces of the p-type semiconductor layer 3, and side surfaces of the second n-type semiconductor layer 4 at inner surfaces of the opening portion to be filled or a surface of the notched portion via the gate insulation film 21. The p-type semiconductor layer 3 has a positive polarization charge at a first n-type semiconductor layer 2 side in a state where a voltage is applied to none of the electrodes.

摘要翻译： 提供能够抑制穿通现象发生的半导体装置。 半导体器件包括衬底1，第一n型半导体层2，p型半导体层3，第二n型半导体层4，漏极13，源电极11，栅电极12和 栅极绝缘膜21，其中第一n型半导体层2，p型半导体层3和第二n型半导体层4依次层压在基板1上。 漏电极13与第一n型半导体层2欧姆接触。源电极11与第二n型半导体层4欧姆接触。要填充的开口部分或延伸的缺口部分 从第二n型半导体层4的上表面到第一n型半导体层2的上部形成在p型半导体层3的一部分上，第二n型半导体层的一部分 栅电极12与第一n型半导体层2的上表面，p型半导体层3的侧表面和第二n型半导体层4的内表面的侧表面接触 待填充的开口部分或经由栅极绝缘膜21的切口部分的表面。在施加电压的状态下，p型半导体层3在第一n型半导体层2侧具有正极化电荷 没有电极。

公开(公告)号：US20110284865A1

公开(公告)日：2011-11-24

申请号：US13141449

申请日：2009-12-25

申请人： Takashi Inoue ,  Hironobu Miyamoto ,  Kazuki Ota ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Yuji Ando

发明人： Takashi Inoue ,  Hironobu Miyamoto ,  Kazuki Ota ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Yuji Ando

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/7787 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/66462

摘要： A heterojunction filed effect transistor with a low access resistance, a low on resistance, and the like, a method for producing a heterojunction filed effect transistor and an electron device are provided. In the heterojunction field effect transistor, an electron transit layer 11 formed of a III-nitride semiconductor is formed on a substrate 10, an electron supply layer 12 formed of a III-nitride semiconductor forms a heterojunction with an upper surface of the electron transit layer 11, a gate electrode 14, a source electrode 15A, and a drain electrode 15B are arranged on the electron supply layer 12, n-type conductive layer regions 13A and 13B each extended from an upper part of the electron transit layer 11 to an upper surface of the electron supply layer 12 are provided in at least a part below the source electrode 15A and a part below the drain electrode 15B, and an n-type impurity concentration at a heterojunction interface of an electron transit layer 11 part of each of the n-type conductive layer regions 13A and 13B with the electron supply layer 12 is 1×1020 cm−3 or more.

摘要翻译： 提供具有低访问阻抗，低导通电阻等的异质结场效应晶体管，提供了异质结场效应晶体管和电子器件的制造方法。 在异质结场效应晶体管中，在衬底10上形成由III族氮化物半导体形成的电子迁移层11，由III族氮化物半导体形成的电子供给层12与电子迁移层的上表面形成异质结 如图11所示，在电子供给层12上配置有栅电极14，源电极15A和漏电极15B，从电子渡越层11的上部延伸到上部的n型导电层区域13A，13B 电子供给层12的表面设置在源电极15A的下方以及漏电极15B的下方的至少一部分以及电子迁移层11的异质界面的n型杂质浓度 具有电子供给层12的n型导电层区域13A，13B为1×1020cm-3以上。

公开(公告)号：US07800131B2

公开(公告)日：2010-09-21

申请号：US11921857

申请日：2006-06-12

申请人： Hironobu Miyamoto ,  Yuji Ando ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Akio Wakejima ,  Kensuke Kasahara ,  Yasuhiro Murase ,  Kohji Matsunaga ,  Katsumi Yamanoguchi ,  Hidenori Shimawaki

发明人： Hironobu Miyamoto ,  Yuji Ando ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota ,  Akio Wakejima ,  Kensuke Kasahara ,  Yasuhiro Murase ,  Kohji Matsunaga ,  Katsumi Yamanoguchi ,  Hidenori Shimawaki

IPC分类号： H01L29/812 ,  H01L21/338

CPC分类号： H01L29/404 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/802 ,  H01L29/812

摘要： A field effect transistor includes a layer structure made of compound semiconductor (111) provided on a semiconductor substrate (110) made of GaAs or InP, as an operation layer, and employs a first field plate electrode (116) and a second field plate electrode (118). The second field plate electrode includes a shielding part (119) located in the region between the first field plate electrode and a drain electrode (114), and serves to shield the first field plate electrode from the drain electrode. When, in the cross sectional view in the gate length direction, the length in the gate length direction of an overlap region, in which the second field plate electrode overlaps the upper part of a structure composed of the first field plate electrode and a gate electrode (113), is designated as Lol, and the gate length is Lg, the relation expressed as 0≦Lol/Lg≦1 holds.

摘要翻译： 场效应晶体管包括由设置在由GaAs或InP制成的半导体衬底（110）上的化合物半导体（111）作为操作层的层结构，并且采用第一场极板电极（116）和第二场极板电极 （118）。 第二场板电极包括位于第一场极板电极和漏电极（114）之间的区域中的屏蔽部分（119），用于屏蔽第一场极板电极与漏极电极。 当在栅极长度方向的截面图中，重叠区域的栅极长度方向上的长度，其中第二场极板电极与由第一场极板电极和栅电极构成的结构的上部重叠 （113）表示为Lol，栅极长度为Lg，表示为0＆nlE; Lol / Lg＆nlE; 1的关系成立。

公开(公告)号：US20090173968A1

公开(公告)日：2009-07-09

申请号：US12097700

申请日：2006-12-12

申请人： Kouji Matsunaga ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Akio Wakejima ,  Yuji Ando ,  Hironobu Miyamoto ,  Takashi Inoue ,  Yasuhiro Murase

发明人： Kouji Matsunaga ,  Kazuki Ota ,  Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Akio Wakejima ,  Yuji Ando ,  Hironobu Miyamoto ,  Takashi Inoue ,  Yasuhiro Murase

IPC分类号： H01L29/205

CPC分类号： H01L29/7787 ,  H01L29/2003 ,  H01L29/66462

摘要： A semiconductor device 100 contains an undoped GaN channel layer 105, an AlGaN electron donor layer 106 provided on the undoped GaN channel layer 105 as being brought into contact therewith, an undoped GaN layer 107 provided on the AlGaN electron donor layer 106, a source electrode 101 and a drain electrode 103 provided on the undoped GaN layer 107 as being spaced from each other, a recess 111 provided in the region between the source electrode 101 and the drain electrode 103, as being extended through the undoped GaN layer 107, a gate electrode 102 buried in the recess 111 as being brought into contact with the AlGaN electron donor layer 106 on the bottom surface thereof, and an SiN film 108 provided on the undoped GaN layer 107, in the region between the gate electrode 102 and the drain electrode 103.

摘要翻译： 半导体器件100包含未掺杂的GaN沟道层105，设置在与其接触的未掺杂的GaN沟道层105上的AlGaN电子供体层106，设置在AlGaN电子供体层106上的未掺杂的GaN层107，源电极 101和设置在未掺杂的GaN层107上彼此间隔开的漏电极103，设置在源电极101和漏电极103之间的区域中的凹槽111延伸穿过未掺杂的GaN层107，栅极 埋入凹槽111中的电极102与其底表面上的AlGaN电子供体层106接触，以及设置在未掺杂的GaN层107上的SiN膜108，在栅电极102和漏极之间的区域 103。

公开(公告)号：US08674409B2

公开(公告)日：2014-03-18

申请号：US13141449

申请日：2009-12-25

申请人： Takashi Inoue ,  Hironobu Miyamoto ,  Kazuki Ota ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Yuji Ando

发明人： Takashi Inoue ,  Hironobu Miyamoto ,  Kazuki Ota ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Yuji Ando

IPC分类号： H01L29/66

CPC分类号： H01L29/7787 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/42316 ,  H01L29/66462

摘要： A heterojunction filed effect transistor with a low access resistance, a low on resistance, and the like, a method for producing a heterojunction filed effect transistor and an electron device are provided. In the heterojunction field effect transistor, an electron transit layer 11 formed of a III-nitride semiconductor is formed on a substrate 10, an electron supply layer 12 formed of a III-nitride semiconductor forms a heterojunction with an upper surface of the electron transit layer 11, a gate electrode 14, a source electrode 15A, and a drain electrode 15B are arranged on the electron supply layer 12, n-type conductive layer regions 13A and 13B each extended from an upper part of the electron transit layer 11 to an upper surface of the electron supply layer 12 are provided in at least a part below the source electrode 15A and a part below the drain electrode 15B, and an n-type impurity concentration at a heterojunction interface of an electron transit layer 11 part of each of the n-type conductive layer regions 13A and 13B with the electron supply layer 12 is 1×1020 cm−3 or more.

摘要翻译： 提供具有低访问阻抗，低导通电阻等的异质结场效应晶体管，提供了异质结场效应晶体管和电子器件的制造方法。 在异质结场效应晶体管中，在衬底10上形成由III族氮化物半导体形成的电子迁移层11，由III族氮化物半导体形成的电子供给层12与电子迁移层的上表面形成异质结 如图11所示，在电子供给层12上配置有栅电极14，源电极15A和漏电极15B，从电子渡越层11的上部延伸到上部的n型导电层区域13A，13B 电子供给层12的表面设置在源电极15A的下方以及漏电极15B的下方的至少一部分以及电子迁移层11的异质界面的n型杂质浓度 具有电子供给层12的n型导电层区域13A，13B为1×1020cm-3以上。

公开(公告)号：US08198652B2

公开(公告)日：2012-06-12

申请号：US12295004

申请日：2007-03-29

申请人： Yuji Ando ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Yasuhiro Murase ,  Kazuki Ota ,  Akio Wakejima ,  Naotaka Kuroda

发明人： Yuji Ando ,  Hironobu Miyamoto ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Yasuhiro Murase ,  Kazuki Ota ,  Akio Wakejima ,  Naotaka Kuroda

IPC分类号： H01L29/80

CPC分类号： H01L29/7787 ,  H01L29/2003

摘要： Disclosed is an HJFET 110 which comprises: a channel layer 12 composed of InyGa1-yN (0≦y≦1); a carrier supply layer 13 composed of AlxGa1-xN (0≦x≦1), the carrier supply layer 13 being provided over the channel layer 12 and including at least one p-type layer; and a source electrode 15S, a drain electrode 15D and a gate electrode 17 which are disposed facing the channel layer 12 through the p-type layer, and provided over the carrier supply layer 13. The following relational expression is satisfied: 5.6×1011x

摘要翻译： 公开了一种HJFET 110，其包括：由In y Ga 1-y N（0＆lt; n 1; y＆n 1; 1）构成的沟道层12; 载体供给层13由Al x Ga 1-x N（0＆lt; n 1; x＆n 1; 1）组成，载流子供给层13设置在沟道层12上并且包括至少一个p型层; 以及源极电极15S，漏极电极15D和栅极电极17，其通过p型层面对沟道层12，并且设置在载流子供给层13上。满足以下关系式：5.6×10 11× NA×＆eegr×T [cm-2] <5.6×1013x，其中x表示载流子供应层的Al组成比，t表示p型层的厚度，NA表示杂质浓度，＆eegr; 表示活化比。