Abstract:
A hydrocarbon synthesis reaction apparatus which synthesizes a hydrocarbon compound by a chemical reaction of a synthesis gas including hydrogen and carbon monoxide as the main components, and a slurry having solid catalyst particles suspended in a liquid, the hydrocarbon synthesis reaction apparatus is provided with: a reactor which contains the slurry; a synthesis gas introduction part which introduces the synthesis gas into the reactor; and a synthesis gas heating part which is provided in the synthesis gas introduction part to heat the synthesis gas introduced into the reactor to the decomposition temperature of carbonyl compounds or higher.
Abstract:
A catalyst separation system is provided with: a reactor where hydrocarbons are synthesized by a chemical reaction of a synthesis gas including carbon monoxide gas and hydrogen gas as main components, and a catalyst slurry having solid catalyst particles suspended in a liquid; filters which separate the hydrocarbons and the catalyst slurry; and a gas-liquid separator which separates the liquid hydrocarbons flowing out of the filter into gas hydrocarbons and liquid hydrocarbons.
Abstract:
A catalyst separation system which separates catalyst particles from liquid hydrocarbons synthesized by a chemical reaction of a synthesis gas including a hydrogen and a carbon monoxide as the main components, and a slurry having solid catalyst particles suspended in a liquid, the catalyst separation system is provided with: a reactor; a storage tank which stores the slurry drawn from the reactor; a plurality of filters which filters the slurry; and a filtrate recovery vessel which recovers a filtrate which has passed through the plurality of filters, wherein the plurality of filters is disposed in series in a flow line for the slurry from the storage tank to the filtrate recovery vessel.
Abstract:
The data memory cell array and parity memory cell array in the memory cell array has a constitution that is capable of corresponding with a plurality of ECC code lengths. An input-side parity generation circuit that generates parities from write data, an output-side parity generation circuit that generates parities from read data, and a syndrome generation circuit that generates a syndrome bit that indicates an error bit from the read parity bits and generated parity bits are constituted so as to be capable of switching, according to the plurality of ECC code lengths.
Abstract:
A hydrocarbon compound synthesis reaction unit which synthesizes a hydrocarbon compound by a chemical reaction of a synthesis gas including a hydrogen and a carbon monoxide as the main components, and a slurry having a solid catalyst suspended in liquid hydrocarbons, the hydrocarbon compound synthesis reaction unit is provided with: a reactor which contains the slurry inside, into which the synthesis gas is introduced, and from which the gas after the reaction is discharged from the top thereof; an internal separation device provided inside the reactor to separate the catalyst and the synthesized liquid hydrocarbons in the slurry; and an external separation device provided outside the reactor to separate the catalyst and the liquid hydrocarbons in the slurry which is extracted from the reactor.
Abstract:
There is provided a synthesis reaction system which synthesizes a hydrocarbon compound by a chemical reaction of a synthesis gas including hydrogen and carbon monoxide as main components, and a slurry having solid catalyst particles suspended in liquid and which extracts the hydrocarbon compound from the slurry. The synthesis reaction system includes a reactor main body which accommodates the slurry, a separator which separates the hydrocarbon compound included in the slurry from the slurry, a first flow passage which allows the slurry including the hydrocarbon compound to flow to the separator from the reactor main body, a second flow passage which allows the slurry to flow to the reactor main body from the separator, and a fluid supply nozzle which supplies a fluid toward at least any one of the separator, the first flow passage, and the second flow passage.
Abstract:
Provided is a solder material test method that reduces labor and time and is preferred in operation hygiene. Detected are a first intensity at a particular wave number of infrared radiation reflected from a test-sample solder material by illuminating light to the test-sample solder material and a second intensity at the particular wave number of infrared radiation reflected from a comparative-sample solder material by illuminating light to the comparative-sample solder material. Depending upon the first and second intensities detected, intensity differences and ratios are determined. Those may be absorbance differences or intensities of between an infrared radiation absorbance to test-sample solder material and an infrared radiation absorbance to comparative-sample solder material. From the intensity difference, intensity ratio, absorbance difference and absorbance ratio, the test-sample solder material is tested for deterioration degree relatively to the comparative sample.
Abstract:
The data memory cell array and parity memory cell array in the memory cell array has a constitution that is capable of corresponding with a plurality of ECC code lengths. An input-side parity generation circuit that generates parities from write data, an output-side parity generation circuit that generates parities from read data, and a syndrome generation circuit that generates a syndrome bit that indicates an error bit from the read parity bits and generated parity bits are constituted so as to be capable of switching, according to the plurality of ECC code lengths.
Abstract:
A memory system that can enhance yield without increasing the chip size and without degrading the access time. A single-bit error determination circuit references parity bits required to configure a code capable of correcting a single-bit error, and determines a single-bit error to be corrected; and a double-bit error detection circuit references one redundant bit added to the parity bits, detects a double-bit error, and enables or disables the double-bit error detection in accordance with a selection signal.
Abstract:
A plasma processing apparatus includes a stock unit, a processing unit, and an alignment chamber. The stock unit supplies and collects a conveyable tray formed with a plurality of housing holes in each of which a wafer is housed. In the processing chamber, plasma processing is executed on the wafers housed in the tray supplied from the stock unit. The alignment chamber is provided with a rotating table on which the tray before being subjected to the plasma processing is set to perform positioning of the wafers on the rotating table. A housing state determination unit of a control device determines whether or not the wafer is misaligned with respect the housing hole of the tray based on a height detected by height detecting sensors.