公开(公告)号：US08908341B2

公开(公告)日：2014-12-09

申请号：US13439426

申请日：2012-04-04

申请人： Manjunatha Prabhu ,  Mahadeva Iyer Natarajan ,  Da-Wei Lai ,  Shan Ryan

发明人： Manjunatha Prabhu ,  Mahadeva Iyer Natarajan ,  Da-Wei Lai ,  Shan Ryan

IPC分类号： H02H9/00 ,  H02H9/04 ,  H02H3/20 ,  H02H3/22

CPC分类号： H02H9/046

摘要： A clamp circuit includes both nmos and pmos devices connected in series between a voltage source terminal, such as an integrated circuit pad, and ground. A trigger unit, connected between the voltage source and ground, includes a plurality of output terminals coupled to the clamp circuit. The trigger unit is responsive to a voltage threshold, such as caused by an ESD occurrence, between the voltage source and ground to apply clamping signals at its output terminals to couple the voltage source terminal to ground through both nmos and pmos devices.

摘要翻译： 钳位电路包括串联连接在诸如集成电路板的电压源端子和地之间的nmos和pmos器件。 连接在电压源和地之间的触发单元包括耦合到钳位电路的多个输出端子。 触发单元响应于电压源和地之间的电压阈值，例如由ESD发生引起的电压阈值，以在其输出端施加钳位信号，以通过nmos和pmos器件将电压源端子耦合到地。

公开(公告)号：US08823129B2

公开(公告)日：2014-09-02

申请号：US12797782

申请日：2010-06-10

申请人： Da-Wei Lai ,  Jen-Chou Tseng ,  Chien-Yuan Lee

发明人： Da-Wei Lai ,  Jen-Chou Tseng ,  Chien-Yuan Lee

IPC分类号： H01L27/105 ,  H01L27/092 ,  H01L29/06 ,  H01L27/118

CPC分类号： H01L27/0921 ,  H01L29/0642 ,  H01L2027/11892 ,  H01L2924/0002 ,  H01L2924/00

摘要： A latch-up prevention structure and method for ultra-small high voltage tolerant cell is provided. In one embodiment, the integrated circuit includes an input and/or output pad, a floating high-voltage n-well (HVNW) connected to the input and/or output pad through a P+ in the floating HVNW and also connected to a first voltage supply, a low-voltage n-well (LVNW) connected to a second voltage supply through a N+ in the LVNW, a HVNW control circuit, and a guard-ring HVNW, where the first voltage supply has higher voltage level than the second voltage supply, guard-ring HVNW is inserted in between the floating HVNW and LVNW to prevent a latch-up path between a P+ in HVNW and N+ in LVNW by using the HVNW control circuit that controls the guard-ring HVNW's voltage level. The guard-ring HVNW's voltage level is matched by the floating HVNW's voltage level.

摘要翻译： 提供了一种用于超小型高耐压单元的闭锁预防结构和方法。 在一个实施例中，集成电路包括通过浮动HVNW中的P +连接到输入和/或输出焊盘的输入和/或输出焊盘，浮动高压n阱（HVNW），并且还连接到第一电压 提供通过LVNW中的N +连接到第二电压源的低电压n阱（LVNW），HVNW控制电路和保护环HVNW，其中第一电压源具有比第二电压更高的电压电平 电源，保护环HVNW插入在浮动HVNW和LVNW之间，以防止HVNW中的P +与LVNW中的N +之间的闩锁路径，通过使用控制保护环HVNW的电压电平的HVNW控制电路。 保护环HVNW的电压电平与浮动HVNW的电压电平相匹配。

公开(公告)号：US20130265676A1

公开(公告)日：2013-10-10

申请号：US13439426

申请日：2012-04-04

申请人： Manjunatha Prabhu ,  Mahadeva Iyer Natarajan ,  Da-Wei Lai ,  Shan Ryan

发明人： Manjunatha Prabhu ,  Mahadeva Iyer Natarajan ,  Da-Wei Lai ,  Shan Ryan

IPC分类号： H02H9/04

CPC分类号： H02H9/046

摘要： A clamp circuit includes both nmos and pmos devices connected in series between a voltage source terminal, such as an integrated circuit pad, and ground. A trigger unit, connected between the voltage source and ground, includes a plurality of output terminals coupled to the clamp circuit. The trigger unit is responsive to a voltage threshold, such as caused by an ESD occurrence, between the voltage source and ground to apply clamping signals at its output terminals to couple the voltage source terminal to ground through both nmos and pmos devices.

摘要翻译： 钳位电路包括串联连接在诸如集成电路板的电压源端子和地之间的nmos和pmos器件。 连接在电压源和地之间的触发单元包括耦合到钳位电路的多个输出端子。 触发单元响应于电压源和地之间的电压阈值，例如由ESD发生引起的电压阈值，以在其输出端施加钳位信号，以通过nmos和pmos器件将电压源端子耦合到地。

公开(公告)号：US08400742B2

公开(公告)日：2013-03-19

申请号：US12824571

申请日：2010-06-28

申请人： Da-Wei Lai ,  Wade Ma

发明人： Da-Wei Lai ,  Wade Ma

IPC分类号： H02H9/00

CPC分类号： H02H9/046

摘要： An electrostatic discharge (ESD) protection circuit coupled with an input/output (I/O) pad. The ESD protection circuit includes a clamp field effect transistor (FET) coupled between a first supply voltage and a second supply voltage. An inverter includes an input end and an output end. The output end of the inverter is coupled with a gate of the clamp FET. A RC time constant circuit is disposed between the first supply voltage and the second supply voltage. A current mirror includes a first transistor. The current mirror is coupled between the input end of the inverter and the second supply voltage. A circuit is coupled with the input end of the inverter. The circuit is capable of outputting a voltage state on the input end of the inverter that is capable of substantially turning off the clamp FET while the I/O pad is subjected to a latch-up test using a negative current.

摘要翻译： 与输入/输出（I / O）接口耦合的静电放电（ESD）保护电路。 ESD保护电路包括耦合在第一电源电压和第二电源电压之间的钳位场效应晶体管（FET）。 逆变器包括输入端和输出端。 反相器的输出端与钳位FET的栅极耦合。 RC时间常数电路设置在第一电源电压和第二电源电压之间。 电流镜包括第一晶体管。 电流镜耦合在反相器的输入端和第二电源电压之间。 电路与逆变器的输入端耦合。 该电路能够在逆变器的输入端输出电压状态，该电压状态能够在使用负电流对I / O焊盘进行闩锁测试的同时基本上关断钳位FET。

公开(公告)号：US08009399B2

公开(公告)日：2011-08-30

申请号：US12548586

申请日：2009-08-27

申请人： Da-Wei Lai

发明人： Da-Wei Lai

IPC分类号： H02H9/00 ,  H02H7/12 ,  H02H1/00 ,  H02H1/04 ,  H02H3/22

CPC分类号： H01L27/0266

摘要： In some embodiments, an electrostatic discharge (ESD) protection circuit includes a substrate resistance control circuit coupled to a body of a first NMOS transistor. The substrate resistance control circuit increases a resistance of the body of the first NMOS transistor during an ESD event. The first NMOS transistor has a drain coupled to an input/output (I/O) pad and a gate coupled to a first voltage source. The first voltage source is set at ground potential.

摘要翻译： 在一些实施例中，静电放电（ESD）保护电路包括耦合到第一NMOS晶体管的主体的衬底电阻控制电路。 衬底电阻控制电路在ESD事件期间增加了第一NMOS晶体管的主体的电阻。 第一NMOS晶体管具有耦合到输入/输出（I / O）焊盘和耦合到第一电压源的栅极的漏极。 第一个电压源设置在地电位。

公开(公告)号：US09154122B2

公开(公告)日：2015-10-06

申请号：US13406534

申请日：2012-02-28

申请人： Da-Wei Lai ,  Mahadeva Iyer Natarajan

发明人： Da-Wei Lai ,  Mahadeva Iyer Natarajan

IPC分类号： H03K17/082 ,  H01L23/62 ,  H01L27/092

CPC分类号： H03K17/082 ,  H01L23/62 ,  H01L27/0921 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device is presented. The device includes a first circuit coupled to first and second power rails of the device. The first circuit is subject to a latch up event in the presence of a latch up condition. The latch up event includes a low resistance path created between the first and second power rails. The device also includes a latch up sensing (LUS) circuit coupled to the first circuit. The LUS circuit is configured to receive a LUS input signal from the first circuit and generates a LUS output signal to the first circuit. When the input signal is an active latch up signal which indicates the presence of a latch up condition, the LUS circuit generates an active LUS output signal which creates a break in the low resistance path to terminate the latch up event.

摘要翻译： 提供了一个设备。 该装置包括耦合到该装置的第一和第二电力轨的第一电路。 在存在闩锁状态的情况下，第一电路经历闩锁事件。 闩锁事件包括在第一和第二电源轨之间产生的低电阻路径。 该装置还包括耦合到第一电路的闭锁检测（LUS）电路。 LUS电路被配置为从第一电路接收LUS输入信号并且产生到第一电路的LUS输出信号。 当输入信号是指示存在锁存状态的有效锁存信号时，LUS电路产生有效的LUS输出信号，该信号在低电阻路径中产生中断以终止锁存事件。

公开(公告)号：US09040367B2

公开(公告)日：2015-05-26

申请号：US13590561

申请日：2012-08-21

申请人： Da-Wei Lai

发明人： Da-Wei Lai

IPC分类号： H01L21/00 ,  H01L29/78 ,  H01L27/02 ,  H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L27/027 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1087 ,  H01L29/41775 ,  H01L29/4933 ,  H01L29/66681 ,  H01L29/7801 ,  H01L29/7816

摘要： An improved nLDMOS ESD protection device having an increased holding voltage is disclosed. Embodiments include: providing in a substrate a DVNW region; providing a HVPW region in the DVNW region; providing bulk and source regions in the HVPW region; providing a drain region in the DVNW region, separate from the HVPW region; and providing a polysilicon gate over a portion of the HVPW region and the DVNW region.

摘要翻译： 公开了一种具有增加的保持电压的改进的nLDMOS ESD保护装置。 实施例包括：在基板中提供DVNW区域; 在DVNW区域提供HVPW区域; 在HVPW区域提供批量和源区域; 在DVNW区域中提供与HVPW区域分离的漏极区域; 以及在HVPW区域和DVNW区域的一部分上提供多晶硅栅极。

公开(公告)号：US08913357B2

公开(公告)日：2014-12-16

申请号：US13485932

申请日：2012-06-01

申请人： Da-Wei Lai ,  Mahadeva Iyer Natarajan

发明人： Da-Wei Lai ,  Mahadeva Iyer Natarajan

IPC分类号： H02H9/04

CPC分类号： H01L27/0248 ,  H01L27/0259 ,  H02H9/04 ,  H02H9/041 ,  H02H9/042 ,  Y10T29/49224

摘要： An ESD circuit is disclosed. The ESD circuit includes a pad and a ground and a sensing element coupled between the pad and ground for sensing an ESD current. The sensing element generates an active sense output signal when an ESD current is sensed and an inactive sense output signal when no ESD current is sensed. The ESD circuit also includes a bypass element comprising a bi-polar junction transistor. The bypass element is coupled in parallel to the sensing element between the pad and ground. The active sense output signal causes the bypass element to be activated to provide a current path between the pad and ground.

摘要翻译： 公开了ESD电路。 ESD电路包括焊盘和接地以及耦合在焊盘和接地之间以感测ESD电流的感测元件。 当感测到ESD电流时，感测元件产生有源感测输出信号，而当感测不到ESD电流时，感测元件产生无源感测输出信号。 ESD电路还包括包括双极结型晶体管的旁路元件。 旁路元件与焊盘和接地之间的感测元件并联耦合。 主动感测输出信号使旁路元件被激活，以提供垫和地之间的电流路径。

公开(公告)号：US08778743B2

公开(公告)日：2014-07-15

申请号：US13588014

申请日：2012-08-17

申请人： Da-Wei Lai ,  Mahadeva Iyer Natarajan

发明人： Da-Wei Lai ,  Mahadeva Iyer Natarajan

IPC分类号： H01L21/332 ,  H01L23/62

CPC分类号： H01L29/7436

摘要： An approach for providing a latch-up robust PNP-triggered SCR-based device is disclosed. Embodiments include providing a silicon control rectifier (SCR) region; providing a PNP region having a first n-well region proximate the SCR region, a first N+ region and a first P+ region in the first n-well region, and a second P+ region between the SCR region and the first n-well region; coupling the first N+ region and the first P+ region to a power rail; and coupling the second P+ region to a ground rail.

摘要翻译： 本发明公开了一种用于提供可靠的PNP触发的基于SCR的器件的方法。 实施例包括提供硅控整流器（SCR）区域; 提供具有靠近SCR区域的第一n阱区域的PNP区域，第一n阱区域中的第一N +区域和第一P +区域以及SCR区域和第一n阱区域之间的第二P +区域; 将第一N +区域和第一P +区域耦合到电力轨道; 以及将所述第二P +区域耦合到地轨。