公开(公告)号：US4896302A

公开(公告)日：1990-01-23

申请号：US277392

申请日：1988-11-22

申请人： Kimiaki Sato ,  Yoshihiro Takemae ,  Masao Nakano ,  Nobumi Kodama

发明人： Kimiaki Sato ,  Yoshihiro Takemae ,  Masao Nakano ,  Nobumi Kodama

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C7/12 ,  G11C8/10 ,  G11C11/401 ,  G11C11/407

CPC分类号： G11C8/10 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/12

摘要： In a semiconductor memory device, a decoder circuit is located between first and second memory cell arrays. A sequence of driver circuits in the decoder circuit is provided as driver circuits common to the first and second memory cell arrays. The output terminal of the driver circuit is connected directly with a data input/output portion for the first memory cell array and connected with another data input/output portion for the second memory cell array through wirings traversing the decoder circuit.

摘要翻译： 在半导体存储器件中，解码器电路位于第一和第二存储单元阵列之间。 解码器电路中的一系列驱动电路被提供为第一和第二存储单元阵列共用的驱动电路。 驱动器电路的输出端子直接与用于第一存储单元阵列的数据输入/输出部分连接，并通过穿过解码器电路的布线与第二存储单元阵列的另一数据输入/输出部分相连。

公开(公告)号：US4742486A

公开(公告)日：1988-05-03

申请号：US861199

申请日：1986-05-08

申请人： Yoshihiro Takemae ,  Shigeki Nozaki ,  Masao Nakano ,  Kimiaki Sato ,  Nobumi Kodama

发明人： Yoshihiro Takemae ,  Shigeki Nozaki ,  Masao Nakano ,  Kimiaki Sato ,  Nobumi Kodama

IPC分类号： G06F11/22 ,  G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G06F11/267 ,  G11C11/34 ,  G11C11/401 ,  G11C17/00 ,  G11C29/00 ,  G11C29/14 ,  G11C29/46 ,  G11C13/00

CPC分类号： G01R31/31701 ,  G11C29/46 ,  G06F11/267

摘要： In a semiconductor integrated circuit comprising an internal circuit, a device for receiving a chip select signal from the outside, a device for receiving an input signal from the outside, and a voltage detecting circuit for detecting whether or not the potential of the input signal is higher than a reference potential; the voltage detecting circuit comprises a first device for differentially comparing the potential of the input signal with the reference potential and generating an output potential in accordance with the results of the comparison, a second device for detecting a predetermined edge of the chip select signal so as to trigger the first device, and a third device for latching the output potential of the first device to the third device when the first device is triggered by the second device, the internal circuit being switched from a first mode to a second mode, or vice versa, in accordance with the output potential of the third device.

摘要翻译： 在包括内部电路的半导体集成电路中，用于从外部接收芯片选择信号的装置，用于从外部接收输入信号的装置以及检测输入信号的电位是否为 高于参考电位; 所述电压检测电路包括用于将所述输入信号的电位与所述参考电位进行差分比较并根据所述比较结果产生输出电位的第一装置，用于检测所述芯片选择信号的预定边沿的第二装置，以便 触发第一装置，以及第三装置，用于当第一装置被第二装置触发时将第一装置的输出电位锁定到第三装置，内部电路从第一模式切换到第二模式，或者副 反之亦然，根据第三器件的输出电位。

公开(公告)号：US20110270424A1

公开(公告)日：2011-11-03

申请号：US13144037

申请日：2009-08-11

申请人： Satoru Nakai ,  Hirohisa Furuta ,  Akira Ishihara ,  Kimiaki Sato ,  Takashi Tsuboi ,  Akira Kaneko

发明人： Satoru Nakai ,  Hirohisa Furuta ,  Akira Ishihara ,  Kimiaki Sato ,  Takashi Tsuboi ,  Akira Kaneko

IPC分类号： G05B19/00

CPC分类号： G06F11/3604 ,  Y02P90/265

摘要： A program analysis support device that can freely combine program analysis conditions and can realize desired program analysis. An analysis condition setting part inputs a program analysis condition in a form of a conditional equation (analysis command, an analysis subject, and analysis condition) having an inherent equation number. A POU list extraction processing executing part executes an analysis command that reads a program to generate a collection of POUs serving as analysis subjects constituting the program, and a variable use list extraction processing executing part executes an analysis command that extracts a cross-reference of a variable to extract a cross-reference of a variable to the POU collection serving as the analysis subject. Both the parts further extract a cross-reference of a variable to another POU collection. An AND processing part further performs processing of a logical product of the cross-references of both the variables and outputs a result thereof to an analysis result display part.

摘要翻译： 程序分析支持设备可以自由组合程序分析条件，并可实现所需的程序分析。 分析条件设置部分以具有固有方程数的条件方程式（分析命令，分析对象和分析条件）的形式输入程序分析条件。 POU列表提取处理执行部执行读取程序以生成构成程序的分析对象的POU的集合的分析命令，并且可变使用列表提取处理执行部执行分析命令，该分析命令提取 变量将变量的交叉引用提取为用作分析对象的POU集合。 这两个部分进一步提取一个变量的交叉引用到另一个POU集合。 AND处理部分进一步执行两个变量的交叉引用的逻辑积的处理，并将其结果输出到分析结果显示部分。

公开(公告)号：US5858276A

公开(公告)日：1999-01-12

申请号：US906478

申请日：1997-08-05

申请人： Masayuki Iwasaki ,  Kimiaki Sato ,  Akira Sugimoto

发明人： Masayuki Iwasaki ,  Kimiaki Sato ,  Akira Sugimoto

IPC分类号： C09K19/02 ,  C09K19/30 ,  C09K19/06 ,  G02F1/1337

CPC分类号： C09K19/3059 ,  C09K19/02

摘要： A liquid crystal composition for use in a DAP mode liquid crystal display device of a homeotropic structure type contains at least one kind of predetermined tolan derivative. The liquid crystal composition is used for a liquid crystal display device of an active-matrix drive type. The liquid crystal composition is also used for a projection type display. The content of the predetermined tolan derivative is in a range of 3 wt % to 20 wt %.

摘要翻译： 用于垂直结构型的DAP模式液晶显示装置的液晶组合物含有至少一种预定的兰兰衍生物。 液晶组合物用于有源矩阵驱动型的液晶显示装置。 液晶组合物也用于投影型显示。 预定的tolan衍生物的含量在3重量％至20重量％的范围内。

公开(公告)号：US09087151B2

公开(公告)日：2015-07-21

申请号：US13144037

申请日：2009-08-11

申请人： Satoru Nakai ,  Hirohisa Furuta ,  Akira Ishihara ,  Kimiaki Sato ,  Takashi Tsuboi ,  Akira Kaneko

发明人： Satoru Nakai ,  Hirohisa Furuta ,  Akira Ishihara ,  Kimiaki Sato ,  Takashi Tsuboi ,  Akira Kaneko

IPC分类号： G05B19/42 ,  G06F11/36

CPC分类号： G06F11/3604 ,  Y02P90/265

摘要： A program analysis support device that can freely combine program analysis conditions and can realize desired program analysis. An analysis condition setting part inputs a program analysis condition in a form of a conditional equation (analysis command, an analysis subject, and analysis condition) having an inherent equation number. A POU list extraction processing executing part executes an analysis command that reads a program to generate a collection of POUs serving as analysis subjects constituting the program, and a variable use list extraction processing executing part executes an analysis command that extracts a cross-reference of a variable to extract a cross-reference of a variable to the POU collection serving as the analysis subject. Both the parts further extract a cross-reference of a variable to another POU collection. An AND processing part further performs processing of a logical product of the cross-references of both the variables and outputs a result thereof to an analysis result display part.

摘要翻译： 程序分析支持设备可以自由组合程序分析条件，并可实现所需的程序分析。 分析条件设置部分以具有固有方程数的条件方程（分析命令，分析对象和分析条件）的形式输入程序分析条件。 POU列表提取处理执行部执行读取程序以生成构成程序的分析对象的POU的集合的分析命令，并且可变使用列表提取处理执行部执行分析命令，该分析命令提取 变量将变量的交叉引用提取为用作分析对象的POU集合。 这两个部分进一步提取一个变量的交叉引用到另一个POU集合。 AND处理部分进一步执行两个变量的交叉引用的逻辑积的处理，并将其结果输出到分析结果显示部分。

公开(公告)号：US4839868A

公开(公告)日：1989-06-13

申请号：US95199

申请日：1987-09-11

申请人： Kimiaki Sato ,  Tool Khono

发明人： Kimiaki Sato ,  Tool Khono

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C7/18 ,  G11C7/22 ,  G11C11/409

CPC分类号： G11C7/18 ,  G11C7/1075 ,  G11C7/22

摘要： A semiconductor memory device includes a write data transfer unit; a plurality of groups of sense amplifiers; a plurality of word lines; and a plurality of pairs of bit lines. Each of the pairs of bit lines includes a pair of inside bit lines, extending between the write data transfer unit and each of the sense amplifiers, and a pair of outside bit lines, extending from each of the sense amplifiers to the side opposite the side of the write data transfer unit. A plurality of memory cells is connected between the word lines and the pairs of bit lines, respectively. The drive timing of a selected one of the groups of sense amplifiers, connected to the selected one of pairs of bit lines on which the transfer of the write data is being performed, is delayed when compared with the drive timing of the sense amplifiers connected to the remaining pairs of bit lines on which the transfer of the write data is not being performed. The write data is transferred from the write data transfer unit to a part of the memory cells connected to a selected one of outside bit lines connected to the selected one of the groups of sense amplifiers. Further, it is also possible to stop the drive of the selected one of the groups of sense amplifiers connected to the selected one of pairs of bit lines on which the transfer of the write data is being performed, instead of delaying the drive timing of the selected one of the groups of sense amplifiers.

摘要翻译： 半导体存储器件包括写入数据传送单元; 多组读出放大器; 多个字线; 和多对位线。 每对位线包括在写入数据传送单元和每个读出放大器之间延伸的一对内部位线以及从每个读出放大器延伸到与侧面相对的一侧的一对外部位线 的写数据传输单元。 多个存储单元分别连接在字线和位线对之间。 与正在执行写入数据的传送的所选择的一对位线连接的读出放大器组中的所选择的一组的驱动定时与连接到的读出放大器的驱动定时相比延迟 在其上不执行写入数据的传送的剩余的位线对。 写入数据从写入数据传送单元传送到连接到所选择的一组读出放大器的外部位线之一的存储器单元的一部分。 此外，还可以停止连接到正在执行写入数据的传送的所选择的一对位线中的选择的一组读出放大器的驱动，而不是延迟执行写入数据的驱动定时 选择了一组读出放大器。